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regarding the change of names mentioned in the document, such as mitsubishi electric and mitsubishi xx, to renesas technology corp. the semiconductor operations of hitachi and mitsubishi electric were transferred to renesas technology corporation on april 1st 2003. these operations include microcomputer, logic, analog and discrete devices, and memory chips other than drams (flash memory, srams etc.) accordingly, although mitsubishi electric, mitsubishi electric corporation, mitsubishi semiconductors, and other mitsubishi brand names are mentioned in the document, these names have in fact all been changed to renesas technology corp. thank you for your understanding. except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. note : mitsubishi electric will continue the business operations of high frequency & optical devices and power devices. renesas technology corp. customer support dept. april 1, 2003 to all our customers
overview 1 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. overview the m16c/62p group of single-chip microcomputers are built using the high-performance silicon gate cmos process using a m16c/60 series cpu core and are packaged in a 100-pin and 128-pin plastic molded qfp. these single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. with 1m bytes of address space, they are capable of executing instructions at high speed. in addition, this microcomputer contains a multiplier and dmac which combined with fast instruction processing capability, makes it suitable for control of various oa, communication, and industrial equipment which requires high-speed arithmetic/logic operations. applications audio, cameras, office/communications/portable/industrial equipment, etc specifications written in this manual are believed to be accurate, but are not guaranteed to be entirely free of error. specifications in this manual may be changed for functional or performance improvements. please make sure your manual is the latest edition. overview ......................................................... 1 central processing unit (cpu) ..................... 12 special function registers (sfr) ................. 14 reset ............................................................. 20 processor mode ............................................ 29 clock generation circuit ............................... 51 protection ...................................................... 74 interrupts ....................................................... 75 watchdog timer ............................................ 95 dmac ........................................................... 97 timers ......................................................... 107 timer a .................................................... 109 timer b .................................................... 123 three-phase motor control timer function 129 serial i/o ..................................................... 139 clock synchronous serial i/o mode ........ 148 uart mode ............................................. 155 special mode 1 (i 2 c mode) ..................... 162 special mode 2 ........................................ 172 special mode 3 (ie mode) ....................... 177 special mode 4 (sim mode) (uart2) ..... 179 si/o3 and si/o4 .......................................... 184 a-d converter ............................................. 189 d-a converter ............................................. 206 crc calculation ......................................... 208 programmable i/o ports ............................. 210 electrical characteristics ............................. 223 flash memory ............................................. 261 ------table of contents------
overview 2 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. table 1.1.1. performance outline of m16c/62p group performance outline table 1.1.1 lists performance outline of m16c/62p group. item performance number of basic instructions 91 instructions shortest instruction execution time 41.7 ns (f(bclk)= 24mh z , v cc1 = 3.0v to 5.5v) 100 ns (f(bclk)= 10mh z , v cc1 = 2.7v to 5.5v) memory rom (see the product list) capacity ram (see the product list) i/o port 100-pin version 8 bits x 10, 7 bits x 1 p0 to p5: v cc2 ports p0 to p10 (except p8 5 ) p6 to p10: v cc1 ports 128-pin version 8 bits x 13, 7 bits x 1, p0 to p5, p12, p13: v cc2 ports p0 to p14 (except p8 5 ) 2 bits x 1 p6 to p10, p11, p14: v cc1 ports input port p8 5 _______ 1 bit x 1 (nmi pin level judgment): v cc1 ports multifunction timer output 16 bits x 5 channels (ta0, ta1, ta2, ta3, ta40) input 16 bits x 6 channels (tb0, tb1, tb2, tb3, tb4, tb5) serial i/o 3 channels (uart0, uart1, uart2) uart, clock synchronous, i 2 c bus 1 (option 3 ), or ie bus 2 (option 3 ) 2 channels (si/o3, si/o4) clock synchronous a-d converter 10 bits x (8 x 3 + 2) channels d-a converter 8 bits x 2 dmac 2 channels (trigger: 25 sources) crc calculation circuit crc-ccitt watchdog timer 15 bits x 1 (with prescaler) interrupt 25 internal and 8 external sources, 4 software sources, 7 levels clock generation circuit 4 circuits ? main clock ? sub-clock ? ring oscillator (for main-clock oscillation stop detect function) ? pll frequency synthesizer voltage detection circuit present (option 3 ) power supply voltage v cc1 =3.0v to 5.5v, v cc2 =3.0v to v cc1 ( f(bclk)=24mh z ) v cc1 =v cc2 = 2.7v to 5.5v ( f(bclk)=10mh z ) flash memory program/erase voltage 3.3v 0.3v or 5.0v 0.5v number of program/erase 100 times power consumption 14ma (v cc1 =v cc2 =5v, f(bclk)=24mh z ) 8ma (v cc1 =v cc2 =3v, f(bclk)=10mh z ) 1.8 a (v cc1 =v cc2 =3v, f(x cin )=32kh z , when wait mode) i/o i/o withstand voltage 5.0v characteristics output current 5ma memory expansion available (to 4m bytes) operating ambient temperature - 20 to 85 c -40 to 85 c (option 3 ) device configuration cmos high performance silicon gate package 100-pin and 128-pin plastic mold qfp notes: 1. i 2 c bus is a registered trademark of philips. 2. ie bus is a registered trademark of nec. 3. if you desire this option, please so specify. ?? ?? ? ?? ?? ? ?? ?? ? (these circuits contain a built-in feedback resistor and external ceramic/quartz oscillator)
overview 3 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. block diagram figure 1.1.1 is a block diagram of the m16c/62p group. timer (16-bit) output (timer a): 5 input (timer b): 6 internal peripheral functions watchdog timer (15 bits) dmac (2 channels) d-a converter (8 bits x 2 channels) a-d converter (10 bits x 8 channels expandable up to 26 channels) uart or clock synchronous serial i/o (8 bits x 3 channels) system clock generator x in -x out x cin -x cout pll frequency synthesizer ring oscillator m16c/60 series16-bit cpu core port p0 8 port p1 8 port p2 8 port p3 8 port p4 8 port p5 8 port p6 8 crc arithmetic circuit (ccitt ) (polynomial : x 16 +x 12 +x 5 +1) memory 8 7 8 8 port p10 port p9 port p8 port p7 port p8 5 rom (note 1) ram (note 2) note 1: rom size depends on microcomputer type. note 2: ram size depends on microcomputer type. note 3: ports p11 to p14 exist only in 128-pin version. clock synchronous serial i/o (8 bits x 2 channels) r0lr0h r1h r1l r2 r3 sb flg usp isp intb pc multiplier port p11 8 port p14 2 port p12 8 port p13 8 three-phase motor control circuit a0 a1 fb (note 3) (note 3) (note 3) (note 3) figure 1.1.1. block diagram
overview 4 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. product list tables 1.1.2 and 1.1.3 list the m16c/62p group products and figure 1.1.2 shows the type numbers, memory sizes and packages. table 1.1.2. product list (1) ram capacity rom capacity package type remarks type no. as of january 2003 mask rom version * 384k bytes ** m30622mep-xxxfp m30620mcp-xxxfp m30622map-xxxfp m30622m8p-xxxfp m30622m6p-xxxfp 100p6q-a m30622mep-xxxgp m30620mcp-xxxgp m30622map-xxxgp m30622m8p-xxxgp m30622m6p-xxxgp 100p6s-a 100p6q-a 100p6s-a 100p6q-a 100p6s-a 100p6q-a 100p6s-a 100p6q-a 100p6s-a m30623mep-xxxgp 128p6q-a m30624mgp-xxxfp 100p6s-a m30624mgp-xxxgp 100p6q-a m30625mgp-xxxgp 128p6q-a m30622mgp-xxxfp 100p6s-a m30622mgp-xxxgp 100p6q-a 128p6q-a m30623mgp-xxxgp m30626mwp-xxxfp 100p6s-a m30626mwp-xxxgp 100p6q-a 128p6q-a m30627mwp-xxxgp m30624mwp-xxxfp 100p6s-a 100p6q-a m30624mwp-xxxgp 128p6q-a m30625mwp-xxxgp m30622mwp-xxxfp 100p6s-a m30622mwp-xxxgp 100p6q-a m30626mhp-xxxfp 100p6s-a m30626mhp-xxxgp 100p6q-a 128p6q-a m30623mwp-xxxgp 128p6q-a m30627mhp-xxxgp 100p6s-a m30624mhp-xxxfp 100p6q-a m30624mhp-xxxgp 128p6q-a m30625mhp-xxxgp m30622mhp-xxxfp 100p6s-a m30622mhp-xxxgp 100p6q-a 128p6q-a m30623mhp-xxxgp 48k bytes 64k bytes 96k bytes 128k bytes 192k bytes 256k bytes 320k bytes 31k bytes 24k bytes 16k bytes 31k bytes 24k bytes 16k bytes 12k bytes 12k bytes 10k bytes 5k bytes 4k bytes 4k bytes 20k bytes : under planning : under development ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** **
overview 5 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. package type: fp : package 100p6s-a gp : package 100p6q-a, 128p6q-a rom no. omitted for flash memory version and external rom version rom capacity: 6: 48k bytes 8: 64k bytes a: 96k bytes c: 128k bytes e: 192k bytes memory type: m: mask rom version f: flash memory version s: external rom version type no. m 3 0 6 2 6 m h pC x x x f p m16c/62 group m16c family shows ram capacity, pin count, etc (the value itself has no specific meaning) g: 256k bytes w: 320k bytes h: 384k bytes j: 512k bytes figure 1.1.2. type no., memory size, and package m30627fjpgp m30625fgpgp 128p6q-a 100p6s-a m30622f8pfp m30622f8pgp 100p6q-a m30620fcpfp 100p6s-a 100p6q-a m30620fcpgp m30624fgpgp 100p6s-a m30624fgpfp m30626fhpfp 128p6q-a 100p6s-a 100p6q-a m30626fhpgp m30627fhpgp m30626fjpfp 100p6q-a 100p6s-a m30626fjpgp m30620spfp m30620spgp 100p6q-a m30622spfp m30622spgp 128p6q-a 100p6q-a 100p6s-a 100p6q-a 100p6s-a ** ** ** ** * * * * : under planning : under development ** ** ** ** ** ** ** ** ** ** ** 384k bytes 64k bytes 128k bytes 256k bytes 512k bytes ram capacity rom capacity package type remarks type no. as of january 2003 flash memory version external rom version 31k bytes 10k bytes 4k bytes 20k bytes 4k bytes 31k bytes 10k bytes table 1.1.3. product list (2)
overview 6 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. 1 2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 606162 63 64 65 66 6768 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 1 00 p0 0 /an 00 /d 0 p0 1 /an 01 /d 1 p0 2 /an 02 /d 2 p0 3 /an 03 /d 3 p0 4 /an 04 /d 4 p0 5 /an 05 /d 5 p0 6 /an 06 /d 6 p0 7 /an 07 /d 7 p1 0 /d 8 p1 1 /d 9 p1 2 /d 10 p1 3 /d 11 p1 4 /d 12 v ref av ss v cc1 x in x out v ss reset cnvss p8 7 /x cin p8 6 /x cout byte p2 0 /an 20 /a 0 (/d 0 /-) p2 1 /an 21 /a 1 (/d 1 /d 0 ) p2 2 /an 22 /a 2 (/d 2 /d 1 ) p2 3 /an 23 /a 3 (/d 3 /d 2 ) p2 4 /an 24 /a 4 (/d 4 /d 3 ) p2 5 /an 25 /a 5 (/d 5 /d 4 ) p2 6 /an 26 /a 6 (/d 6 /d 5 ) p2 7 /an 27 /a 7 (/d 7 /d 6 ) p3 0 /a 8 (/-/d 7 ) p3 1 /a 9 p3 2 /a 10 p3 3 /a 11 p3 4 /a 12 p3 5 /a 13 p3 6 /a 14 p3 7 /a 15 p4 0 /a 16 p4 1 /a 17 p4 2 /a 18 p4 3 /a 19 p7 4 /ta2 out /w p7 6 /ta3 out p5 6 /ale p7 7 /ta3 in p5 5 /hold p5 4 /hlda p5 3 /bclk p5 2 /rd v cc2 v ss p5 7 /rdy/clk out p4 5 /cs1 p4 6 /cs2 p4 7 /cs3 av cc p6 3 /t x d 0 /sda 0 p6 5 /clk 1 p6 6 /rxd 1 /scl 1 p6 7 /t x d 1 /sda 1 p6 1 /clk 0 p6 2 /rxd 0 /scl 0 p10 0 /an 0 p10 1 /an 1 p10 2 /an 2 p10 3 /an 3 p9 3 /da 0 /tb3 in p9 4 /da 1 /tb4 in p9 5 /anex0/clk4 p9 6 /anex1/s out 4 p9 1 /tb1 in /s in 3 p9 2 /tb2 in /s out 3 p8 0 /ta4 out /u p6 0 /cts 0 /rts 0 p6 4 /cts 1 /rts 1 /cts 0 /clks 1 p7 2 /clk 2 /ta1 out /v p8 2 /int 0 p7 1 /rxd 2 /scl 2 /ta0 in /tb5 in (note) p8 3 /int 1 p8 5 /nmi p9 7 /ad trg /s in 4 p4 4 /cs0 p5 0 /wrl/wr p5 1 /wrh/bhe p9 0 /tb0 in /clk3 p7 0 /t x d 2 /sda 2 /ta0 out (note) p8 4 /int 2 p8 1 /ta4 in /u p7 3 /cts 2 /rts 2 /ta1 in /v p7 5 /ta2 in /w p1 5 /d 13 /int3 p1 6 /d 14 /int4 p1 7 /d 15 /int5 p10 7 /an 7 /ki 3 p10 6 /an 6 /ki 2 p10 5 /an 5 /ki 1 p10 4 /an 4/ ki 0 pin configuration figures 1.1.3 to 1.1.5 show the pin configurations (top view). package: 100p6s-a figure 1.1.3. pin configuration (top view) m16c/62p group pin configuration (top view) note: p7 0 and p7 1 are n channel open-drain output pins.
overview 7 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. 1 2 3 4 5 6 7 8 9 10111213141516171819202122232425 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 606162 63 64 65 66 6768 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 1 00 p0 0 /an 00 /d 0 p0 1 /an 01 /d 1 p0 2 /an 02 /d 2 p0 3 /an 03 /d 3 p0 4 /an 04 /d 4 p0 5 /an 05 /d 5 p0 6 /an 06 /d 6 p0 7 /an 07 /d 7 p1 0 /d 8 p1 1 /d 9 p1 2 /d 10 p1 3 /d 11 p1 4 /d 12 v ref av ss v cc1 x in x out v ss reset cnvss p8 7 /x cin p8 6 /x cout byte p2 0 /an 20 /a 0 (/d 0 /-) p2 1 /an 21 /a 1 (/d 1 /d 0 ) p2 2 /an 22 /a 2 (/d 2 /d 1 ) p2 3 /an 23 /a 3 (/d 3 /d 2 ) p2 4 /an 24 /a 4 (/d 4 /d 3 ) p2 5 /an 25 /a 5 (/d 5 /d 4 ) p2 6 /an 26 /a 6 (/d 6 /d 5 ) p2 7 /an 27 /a 7 (/d 7 /d 6 ) p3 0 /a 8 (/-/d 7 ) p3 1 /a 9 p3 2 /a 10 p3 3 /a 11 p3 4 /a 12 p3 5 /a 13 p3 6 /a 14 p3 7 /a 15 p4 0 /a 16 p4 1 /a 17 p4 2 /a 18 p4 3 /a 19 p7 4 /ta2 out /w p7 6 /ta3 out p5 6 /ale p7 7 /ta3 in p5 5 /hold p5 4 /hlda p5 3 /bclk p5 2 /rd v cc2 v ss p5 7 /rdy/clk out p4 5 /cs1 p4 6 /cs2 p4 7 /cs3 avcc p6 3 /t x d 0 /sda 0 p6 5 /clk 1 p6 6 /rxd 1 /scl 1 p6 7 /t x d 1 /sda 1 p6 1 /clk 0 p6 2 /rxd 0 /scl 0 p10 0 /an 0 p10 1 /an 1 p10 2 /an 2 p10 3 /an 3 p9 3 /da 0 /tb3 in p9 4 /da 1 /tb4 in p9 5 /anex0/clk4 p9 6 /anex1/s out 4 p9 1 /tb1 in /s in 3 p9 2 /tb2 in /s out 3 p8 0 /ta4 out /u p6 0 /cts 0 /rts 0 p6 4 /cts 1 /rts 1 /cts 0 /clks 1 p8 2 /int 0 p8 3 /int 1 p8 5 /nmi p9 7 /ad trg /s in 4 p4 4 /cs0 p5 0 /wrl/wr p5 1 /wrh/bhe p9 0 /tb0 in /clk3 p8 4 /int 2 p7 2 /clk 2 /ta1 out /v p7 1 /rxd 2 /scl 2 /ta0 in /tb5 in (note) p7 0 /t x d 2 /sda 2 /ta0 out (note) p7 5 /ta2 in /w p7 3 /cts 2 /rts 2 /ta1 in /v p1 5 /d 13 /int 3 p1 6 /d 14 /int 4 p1 7 /d 15 /int 5 p10 7 /an 7 /ki 3 p10 6 /an 6 /ki 2 p10 5 /an 5 /ki 1 p10 4 /an 4/ ki 0 p8 1 /ta4 in /u figure 1.1.4. pin configuration (top view) package: 100p6q-a m16c/62p group pin configuration (top view) note: p7 0 and p7 1 are n channel open-drain output pins.
overview 8 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.1.5. pin configuration (top view) package: 128p6q-a pin configuration (top view) 1 2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930 73 74 75 76 77 78 79 80 81 82838485 86 87 88 8990 91 92 93 94 95 96 97 98 99 100 101102 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 104 105 106 107 108 31 32 33 34 35 36 37 666768 69 70 71 72 38 65 64 103 p0 0 /an 00 /d 0 p0 1 /an 01 /d 1 p0 2 /an 02 /d 2 p0 3 /an 03 /d 3 p0 4 /an 04 /d 4 p0 5 /an 05 /d 5 p0 6 /an 06 /d 6 p0 7 /an 07 /d 7 p1 0 /d 8 p1 1 /d 9 p1 2 /d 10 av ss v cc1 x in x out v ss reset cnvss p8 7 /x cin p8 6 /x cout byte p7 4 /ta2 out /w p7 6 /ta3 out p5 6 /ale p7 7 /ta3 in p5 5 /hold p5 4 /hlda p5 3 /bclk p5 2 /rd p5 7 /rdy/clk out p4 7 /cs3 p6 3 /t x d 0 /sda 0 p6 5 /clk 1 p6 6 /rxd 1 /scl 1 p6 7 /t x d 1 /sda 1 p6 1 /clk 0 p6 2 /rxd 0 /scl 0 p10 0 /an 0 p10 1 /an 1 p10 2 /an 2 p10 3 /an 3 p9 3 /da 0 /tb3 in p9 4 /da 1 /tb4 in p9 5 /anex0/clk4 p9 6 /anex1/s out 4 p9 1 /tb1 in /s in 3 p9 2 /tb2 in /s out 3 p8 0 /ta4 out /u p6 0 /cts 0 /rts 0 p6 4 /cts 1 /rts 1 /cts 0 /clks 1 p8 2 /int 0 p8 3 /int 1 p8 5 /nmi p4 5 /cs1 p4 6 /cs2 p4 4 /cs0 p5 0 /wrl/wr p5 1 /wrh/bhe p9 0 /tb0 in /clk3 p7 2 /clk 2 /ta1 out /v p7 1 /rxd 2 /scl 2 /ta0 in /tb5 in (note) p7 0 /t x d 2 /sda 2 /ta0 out (note) p8 4 /int 2 p8 1 /ta4 in /u p7 3 /cts 2 /rts 2 /ta1 in /v p7 5 /ta2 in /w p10 7 /an 7 /ki 3 p10 6 /an 6 /ki 2 p10 5 /an 5 /ki 1 p10 4 /an 4/ ki 0 v ref av cc p9 7 /ad trg /s in 4 p14 1 p14 0 p13 7 p13 6 p13 5 p13 4 p1 3 /d 11 p1 4 /d 12 p2 0 /an 20 /a 0 (/d 0 /-) p2 1 /an 21 /a 1 (/d 1 /d 0 ) p2 2 /an 22 /a 2 (/d 2 /d 1 ) p2 3 /an 23 /a 3 (/d 3 /d 2 ) p2 4 /an 24 /a 4 (/d 4 /d 3 ) p2 5 /an 25 /a 5 (/d 5 /d 4 ) p2 6 /an 26 /a 6 (/d 6 /d 5 ) p2 7 /an 27 /a 7 (/d 7 /d 6 ) p3 0 /a 8 (/-/d 7 ) p3 1 /a 9 p3 2 /a 10 p3 3 /a 11 p3 4 /a 12 p3 5 /a 13 p3 6 /a 14 p3 7 /a 15 p4 0 /a 16 p4 1 /a 17 p4 2 /a 18 p4 3 /a 19 v cc2 v ss p1 5 /d 13 /int3 p1 6 /d 14 /int4 p1 7 /d 15 /int5 p12 4 p12 3 p11 3 p11 2 p11 1 p11 0 v cc1 v ss p13 0 p13 1 p13 2 p13 3 p12 5 p12 6 p12 7 p11 4 p11 5 p11 6 p11 7 p12 2 p12 1 p12 0 m16c/62p group note: p7 0 and p7 1 are n channel open-drain output pins.
overview 9 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. v cc1 , v cc2 , v ss cnv ss x in x out byte av cc av ss v ref p0 0 to p0 7 d 0 to d 7 p1 0 to p1 7 d 8 to d 15 p2 0 to p2 7 a 0 to a 7 a 0 /d 0 to a 7 /d 7 a 0 a 1 /d 0 to a 7 /d 6 p3 0 to p3 7 a 8 to a 15 a 8 /d 7 , a 9 to a 15 p4 0 to p4 7 signal name power supply input cnv ss reset input clock input clock output external data bus width select input analog power supply input reference voltage input i/o port p0 i/o port p1 i/o port p2 i/o port p3 i/o port p4 apply 2.7v to 5.5 v to the v cc1 and v cc2 pins and 0 v to the v ss pin. the vcc apply condition is that v cc2 v cc1 function this pin switches between processor modes. connect this pin to v ss pin when after a reset you want to start operation in single- chip mode (memory expansion mode) or the v cc1 pin when starting operation in microprocessor mode. l on this input resets the microcomputer. these pins are provided for the main clock generating circuit input/ output. connect a ceramic resonator or crystal between the x in and the x out pins. to use an externally derived clock, input it to the x in pin and leave the x out pin open. this pin selects the width of an external data bus. a 16-bit width is selected when this input is l; an 8-bit width is selected when this input is h. this input must be fixed to either h or l. connect this pin to the v ss pin when operating in single-chip mode. this pin is a power supply input for the a-d converter. connect this pin to v cc1 . this pin is a power supply input for the a-d converter. connect this pin to v ss . this pin is a reference voltage input for the a-d converter. this is an 8-bit cmos i/o port. this port has an input/output select direction register, allowing each pin in that port to be directed for input or output individually. if any port is set for input, selection can be made for it in a program whether or not to have a pull-up resistor in 4 bit units. this selection is unavailable in memory extension and microprocessor modes. this port can function as input pins for the a-d converter when so selected in a program. when set as a separate bus, these pins input and output data (d 0 Cd 7 ). this is an 8-bit i/o port equivalent to p0. p1 5 to p1 7 also function as int interrupt input pins as selected by a program. when set as a separate bus, these pins input and output data (d 8 Cd 15 ). this is an 8-bit i/o port equivalent to p0. this port can function as input pins for the a-d converter when so selected in a program. these pins output 8 low-order address bits (a 0 to a 7 ). if the external bus is set as an 8-bit wide multiplexed bus, these pins input and output data (d 0 to d 7 ) and output 8 low-order address bits (a 0 to a 7 ) separated in time by multiplexing. if the external bus is set as a 16-bit wide multiplexed bus, these pins input and output data (d 0 to d 6 ) and output address (a 1 to a 7 ) separated in time by multiplexing. they also output address (a 0 ). this is an 8-bit i/o port equivalent to p0. these pins output 8 middle-order address bits (a 8 to a 15 ). if the external bus is set as a 16-bit wide multiplexed bus, these pins input and output data (d 7 ) and output address (a 8 ) separated in time by multiplexing. they also output address (a 9 to a 15 ). this is an 8-bit i/o port equivalent to p0. pin name input input input output input input input/output input/output input/output input/output i/o type analog power supply input input/output output input/output output input/output input/output output input/output output input/output output output a 16 to a 19 , cs 0 to cs 3 these pins output a 16 to a 19 and cs 0 to cs 3 signals. a 16 to a 19 are 4 high- order address bits. cs 0 to cs 3 are chip select signals used to specify an access space. reset (note) power supply v cc1 v cc2 v cc1 v cc1 v cc2 v cc2 v cc2 v cc2 table 1.1.4 pin description (100-pin and 128-pin packages) (continued) note: in this manual, hereafter, v cc refers to v cc1 unless otherwise noted.
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r overview 10 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. table 1.1.5 pin description (100-pin and 128-pin packages) (continued) signal name function pin name i/o type power supply v cc2 p5 0 to p5 7 wrl / wr, wrh / bhe, rd, bclk, hlda, hold, ale, rdy i/o port p5 input/output v cc1 p6 0 to p6 7 i/o port p6 input/output v cc1 p7 0 to p7 7 i/o port p7 input/output v cc1 p8 0 to p8 4 , p8 7 , p8 5 i/o port p8 i/o port p8 5 input/output input/output input output output output output output input output input this is an 8-bit i/o port equivalent to p0. in single-chip mode, p5 7 in this port outputs a divide-by-8 or divide-by-32 clock of x in or a clock of the same frequency as x cin as selected by program. this is an 8-bit i/o port equivalent to p0. pins in this port also function as uart0 and uart1 i/o pins as selected by program. this is an 8-bit i/o port equivalent to p0 (p7 0 and p7 1 are n channel open-drain output). this port can function as input/output pins for timers a0 to a3 when so selected in a program. furthermore, p7 0 to p7 5 , p7 1 , and p7 2 to p7 5 can also function as input/output pins for uart2, an input pin for timer b5, and output pins for the three-phase motor control timer, respectively. output wrl/wr, wrh/bhe, rd, bclk, hlda, and ale signals. wrl/wr and wrh/bhe are switchable in a program. note that wrl and wrh are always used as a pair, so as wr and bhe. wrl, wrh, and rd selected if the external data bus is 16 bits wide, data are written to even addresses when the wrl signal is low, and written to odd addresses when the wrh signal is low. data are read out when the rd signal is low. wr, bhe, and rd selected data are written when the wr signal is low, or read out when the rd signal is low. odd addresses are accessed when the bhe signal is low. use this mode when the external data bus is 8 bits wide. the microcomputer goes to a hold state when input to the hold pin is held low. while in the hold state, hlda outputs a low level. ale is used to latch the address. while the input level of the rdy pin is low, the bus of the microcomputer goes to a wait state. p8 0 to p8 4 , p8 6 , and p8 7 are i/o ports with the same functions as p0. when so selected in a program, p8 0 to p8 1 and p8 2 to p8 4 can function as input/output pins for timer a4 or output pins for the three-phase motor control timer and int interrupt input pins, respectively. p8 6 and p8 7 , when so selected in a program, both can function as input/output pins for the subclock oscillator circuit. in that case, connect a crystal resonator between p8 6 (x cout pin) and p8 7 (x cin pin). p8 5 is an input-only port shared with nmi. an nmi interrupt is generated when input on this pin changes state from high to low. the nmi function cannot be disabled in a program. a pull-up cannot be set for this pin. this is an 8-bit i/o port equivalent to p0. pins in this port also function as si/o3 and si/o4 i/o pins, timer b0 to b4 input pins, d- a converter output pins, a-d converter input pins, or a-d trigger input pins as selected by program. p9 0 to p9 7 i/o port p9 input/output v cc1 this is an 8-bit i/o port equivalent to p0. pins in this port also function as a-d converter input pins as selected by program. furthermore, p10 4 to p10 7 also function as input pins for the key input interrupt function. p10 0 to p10 7 i/o port p10 input/output v cc1 p8 6 , input/output table 1.1.6 pin description (3) (128-pin package) (continued) p11 0 to p11 7 signal name i/o port p11 pin name i/o type input/output p12 0 to p12 7 i/o port p12 input/output p13 0 to p13 7 i/o port p13 input/output p14 0 , p14 1 i/o port p14 function this is an 8-bit i/o port equivalent to p0. this is an 8-bit i/o port equivalent to p0. this is an 8-bit i/o port equivalent to p0. this is an 2-bit i/o port equivalent to p0. input/output power supply circuit block v cc2 v cc2 v cc1 v cc1
memory 11 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. memory figure 1.2.1 is a memory map of the m16c/62p group. the address space extends the 1m bytes from address 00000 16 to fffff 16 . the internal rom is allocated in a lower address direction beginning with address fffff 16 . for example, a 64-kbyte internal rom is allocated to the addresses from f0000 16 to fffff 16 . the fixed interrupt vector table is allocated to the addresses from fffdc 16 to fffff 16 . therefore, store the start address of each interrupt routine here. the internal ram is allocated in an upper address direction beginning with address 00400 16 . for example, a 10-kbytes internal ram is allocated to the addresses from 00400 16 to 02bff 16 . in addition to storing data, the internal ram also stores the stack used when calling subroutines and when interrupts are gener- ated. the srf is allocated to the addresses from 00000 16 to 003ff 16 . peripheral function control registers are located here. of the sfr, any area which has no functions allocated is reserved for future use and cannot be used by users. the special page vector table is allocated to the addresses from ffe00 16 to fffdb 16 . this vector is used by the jmps or jsrs instruction. for details, refer to the m16c/60 and m16c/20 series software manual. in memory expansion and microprocessor modes, some areas are reserved for future use and cannot be used by users. figure 1.2.1. memory map 00000 16 xxxxx 16 aaaaaa a aaaa a a aaaa a aaaaaa external area internal rom sfr internal ram reserved area reserved area ffe00 16 fffdc 16 fffff 16 note 1: during memory expansion and microprocessor modes, can not be used. note 2: in memory expansion mode, can not be used. note 3: shown here is a memory map for the case where the pm10 bit in the pm1 register is 1 and the pm13 bit in the pm1 register is 1. undefined instruction overflow brk instruction address match single step watchdog timer reset special page vector table dbc nmi 4k bytes 013ff 16 02bff 16 017ff 16 address xxxxx 16 033ff 16 10k bytes 5k bytes 12k bytes size address yyyyy 16 size f0000 16 e8000 16 f4000 16 96k bytes 48k bytes 64k bytes reserved area external area 00400 16 10000 16 27000 16 28000 16 80000 16 yyyyy 16 fffff 16 (note 1) (note 2) e0000 16 256k bytes 128k bytes 192k bytes d0000 16 320k bytes c0000 16 384k bytes b0000 16 a0000 16 512k bytes 80000 16 063ff 16 053ff 16 07fff 16 24k bytes 20k bytes 31k bytes internal ram internal rom 043ff 16 16k bytes
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r central processing unit (cpu) 12 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. central processing unit (cpu) figure 1.3.1 shows the cpu registers. the cpu has 13 registers. of these, r0, r1, r2, r3, a0, a1 and fb comprise a register bank. there are two register banks. figure 1.3.1. central processing unit register (1) data registers (r0, r1, r2 and r3) the r0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. r1 to r3 are the same as r0. the r0 register can be separated between high (r0h) and low (r0l) for use as two 8-bit data registers. r1h and r1l are the same as r0h and r0l. conversely, r2 and r0 can be combined for use as a 32- bit data register (r2r0). r3r1 is the same as r2r0. (2) address registers (a0 and a1) the register a0 consists of 16 bits, and is used for address register indirect addressing and address register relative addressing. they also are used for transfers and logic/logic operations. a1 is the same as a0. in some instructions, registers a1 and a0 can be combined for use as a 32-bit address register (a1a0). data registers (note) address registers (note) frame base registers (note) program counter interrupt table register user stack pointer interrupt stack pointer static base register flag register note: these registers comprise a register bank. there are two register banks. r0h(r0's high bits) b15 b8 b7 b0 r3 intbh usp isp sb aa aa aa aa aa aa a a aaaaaaa aaaaaaa aa aa a a aa aa aa aa aa aa cdzsboiu ipl r0l(r0's low bits) r1h(r1's high bits) r1l(r1's low bits) r2 b31 r3 r2 a1 a0 fb b19 intbl b15 b0 pc b19 b0 b15 b0 flg b15 b0 b15 b0 b7 b8 reserved area carry flag debug flag zero flag sign flag register bank select flag overflow flag interrupt enable flag stack pointer select flag reserved area processor interrupt priority level the upper 4 bits of intb are intbh and the lower 16 bits of intb are intbl.
central processing unit (cpu) 13 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. (3) frame base register (fb) fb is configured with 16 bits, and is used for fb relative addressing. (4) interrupt table register (intb) intb is configured with 20 bits, indicating the start address of an interrupt vector table. (5) program counter (pc) pc is configured with 20 bits, indicating the address of an instruction to be executed. (6) user stack pointer (usp) and interrupt stack pointer (isp) stack pointer (sp) comes in two types: usp and isp, each configured with 16 bits. your desired type of stack pointer (usp or isp) can be selected by the u flag of flg. (7) static base register (sb) sb is configured with 16 bits, and is used for sb relative addressing. (8) flag register (flg) flg consists of 11 bits, indicating the cpu status. ?carry flag (c flag) this flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. ?debug flag (d flag) the d flag is used exclusively for debugging purpose. during normal use, it must be set to 0. ? zero flag (z flag) this flag is set to 1 when an arithmetic operation resulted in 0; otherwise, it is 0. ?sign flag (s flag) this flag is set to 1 when an arithmetic operation resulted in a negative value; otherwise, it is 0 . ?register bank select flag (b flag) register bank 0 is selected when this flag is 0 ; register bank 1 is selected when this flag is 1. ?overflow flag (o flag) this flag is set to 1 when the operation resulted in an overflow; otherwise, it is 0. ?interrupt enable flag (i flag) this flag enables a maskable interrupt. maskable interrupts are disabled when the i flag is 0, and are enabled when the i flag is 1. the i flag is cleared to 0 when the interrupt request is accepted. ?stack pointer select flag (u flag) isp is selected when the u flag is 0; usp is selected when the u flag is 1. the u flag is cleared to 0 when a hardware interrupt request is accepted or an int instruction for software interrupt nos. 0 to 31 is executed. ?processor interrupt priority level (ipl) ipl is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. if a requested interrupt has priority greater than ipl, the interrupt is enabled. ?reserved area when write to this bit, write "0". when read, its content is indeterminate.
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r sfr 14 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. dma0 control register d m0con 0 0000?00 2 dma0 transfer counter tcr0 ?? 16 ?? 16 dma1 control register d m1con 0 0000?00 2 dma1 source pointer sar1 ? ? 16 ?? 16 x? 16 dma1 transfer counter tcr1 ?? 16 ?? 16 dma1 destination pointer dar1 ?? 16 ?? 16 x? 16 watchdog timer start register wdts ?? 16 watchdog timer control register wdc 00?????? 2 (note 4) processor mode register 0 ( note 2) pm0 00000000 2 (cnv ss pin is l) 00000011 2 (cnv ss pin is h) chip select control register csr 0 0000001 2 system clock control register 0 c m0 01001000 2 system clock control register 1 c m1 00100000 2 address match interrupt enable register aier xxxxxx00 2 protect register prcr xx000000 2 processor mode register 1 pm1 00001000 2 dma0 destination pointer d ar0 ? ? 16 ?? 16 x? 16 note 1: the blank areas are reserved and cannot be used by users. note 2: the pm00 and pm01 bits do not change at software reset, watchdog timer reset and oscillation stop detection reset. note 3: the cm20, cm21, and cm27 bits do not change at oscillation stop detection reset. note 4: the wdc5 bit is 0 (cold start) immediately after power-on. it can only be set to 1 in a program. it is set to 0 w hen the input voltag e at the v cc1 pin drops to vdet2 or less while the vc25 bit in the vcr2 register is set to 1 (ram retention limit detection circuit enabl e note 5: this register does not change at software reset, watchdog timer reset and oscillation stop detection reset. x : nothing is mapped to this bit ? : undefined data bank register dbr 0 0 16 oscillation stop detection register (note 3) cm2 0 000x000 2 chip select expansion control register cse 00 16 pll control register 0 plc0 0 001x010 2 processor mode register 2 pm2 xxx00000 2 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 address register symbol after reset address match interrupt register 0 rmad0 00 16 00 16 x0 16 address match interrupt register 1 rmad1 00 16 00 16 x0 16 dma0 source pointer sar0 ?? 16 ?? 16 x? 16 power supply detection register 1 (note 5) vcr1 00001000 2 power supply detection register 2 (note 5) vcr2 00 16 power supply down detection interrupt register d4int 0 0 16
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r sfr 15 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. timer a1 interrupt control register ta1ic xxxx?000 2 uart0 transmit interrupt control register s0tic xxxx?000 2 timer a0 interrupt control register ta0ic xxxx?000 2 timer a2 interrupt control register ta2ic xxxx?000 2 uart0 receive interrupt control register s0ric xxxx?000 2 uart1 transmit interrupt control register s1tic xxxx?000 2 uart1 receive interrupt control register s1ric xxxx?000 2 dma1 interrupt control register dm1ic xxxx?000 2 dma0 interrupt control register dm0ic xxxx?000 2 key input interrupt control register kupic xxxx?000 2 a-d conversion interrupt control register adic xxxx?000 2 uart2 bus collision detection interrupt control register bcnic xxxx?000 2 uart2 transmit interrupt control register s2tic xxxx?000 2 uart2 receive interrupt control register s2ric xxxx?000 2 int1 interrupt control register int1ic xx00?000 2 timer b0 interrupt control register tb0ic xxxx?000 2 timer b2 interrupt control register tb2ic xxxx?000 2 timer a3 interrupt control register ta3ic xxxx?000 2 int2 interrupt control register int2ic xx00?000 2 int0 interrupt control register int0ic xx00?000 2 timer b1 interrupt control register tb1ic xxxx?000 2 timer a4 interrupt control register ta4ic xxxx?000 2 int3 interrupt control register int3ic xx00?000 2 timer b5 interrupt control register tb5ic x xxx?000 2 timer b4 interrupt control register, uart1 bus collision detection interrupt control register tb4ic, u1bcnic xxxx?000 2 timer b3 interrupt control register, uart0 bus collision detection interrupt control register tb3ic, u0bcnic xxxx?000 2 si/o4 interrupt control register (s4ic), int5 interrupt control register s4ic , int5ic xx00?000 2 si/o3 interrupt control register, int4 interrupt control register s3ic , int4ic xx00?000 2 note :the blank areas are reserved and cannot be used by users. x : nothing is mapped to this bit ? : undefined 0040 16 0041 16 0042 16 0043 16 0044 16 0045 16 0046 16 0047 16 0048 16 0049 16 004a 16 004b 16 004c 16 004d 16 004e 16 004f 16 0050 16 0051 16 0052 16 0053 16 0054 16 0055 16 0056 16 0057 16 0058 16 0059 16 005a 16 005b 16 005c 16 005d 16 005e 16 005f 16 0060 16 0061 16 0062 16 0063 16 0064 16 0065 16 0066 16 0067 16 0068 16 0069 16 006a 16 006b 16 006c 16 006d 16 006e 16 006f 16 0070 16 0071 16 0072 16 0073 16 0074 16 0075 16 0076 16 0077 16 0078 16 0079 16 007a 16 007b 16 007c 16 007d 16 007e 16 007f 16 address register symbol after reset
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r sfr 16 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. 0080 16 0081 16 0082 16 0083 16 0084 16 0085 16 0086 16 01b0 16 01b1 16 01b2 16 01b3 16 01b4 16 01b5 16 01b6 16 01b7 16 01b8 16 01b9 16 01ba 16 01bb 16 01bc 16 01bd 16 01be 16 01bf 16 0250 16 0251 16 0252 16 0253 16 0254 16 0255 16 0256 16 0257 16 0258 16 0259 16 025a 16 025b 16 025c 16 025d 16 025e 16 025f 16 0330 16 0331 16 0332 16 0333 16 0334 16 0335 16 0336 16 0337 16 0338 16 0339 16 033a 16 033b 16 033c 16 033d 16 033e 16 033f 16 note 1: the blank areas are reserved and cannot be used by users. note 2: this register is included in the flash memory version. x : nothing is mapped to this bit ? : undefined peripheral clock select register pclkr 0 0000011 2 flash memory control register 0 (note 2) fmr0 ??000001 2 flash memory control register 1 (note 2) fmr1 0?00??0? 2 address match interrupt register 2 rmad2 00 16 00 16 x0 16 address match interrupt register 3 rmad3 00 16 00 16 x0 16 address match interrupt enable register 2 aier2 x xxxxx00 2 address register symbol after reset ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ flash identification register (note 2) fidr xxxxxx00 2
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r sfr 17 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. address register symbol after reset 0340 16 0341 16 0342 16 0343 16 0344 16 0345 16 0346 16 0347 16 0348 16 0349 16 034a 16 034b 16 034c 16 034d 16 034e 16 034f 16 0350 16 0351 16 0352 16 0353 16 0354 16 0355 16 0356 16 0357 16 0358 16 0359 16 035a 16 035b 16 035c 16 035d 16 035e 16 035f 16 0360 16 0361 16 0362 16 0363 16 0364 16 0365 16 0366 16 0367 16 0368 16 0369 16 036a 16 036b 16 036c 16 036d 16 036e 16 036f 16 0370 16 0371 16 0372 16 0373 16 0374 16 0375 16 0376 16 0377 16 0378 16 0379 16 037a 16 037b 16 037c 16 037d 16 037e 16 037f 16 timer a1-1 register ta11 ?? 16 ?? 16 timer a2-1 register ta21 ?? 16 ?? 16 dead time timer dtt ?? 16 timer b2 interrupt occurrence frequency set counter ictb2 ?? 16 three-phase pwm control register 0 invc0 00 16 three-phase pwm control register 1 invc1 00 16 three-phase output buffer register 0 idb0 00 16 three-phase output buffer register 1 idb1 00 16 timer b3 register tb3 ?? 16 ?? 16 timer b4 register tb4 ?? 16 ?? 16 timer b5 register tb5 ?? 16 ?? 16 timer b3, 4, 5 count start flag tbsr 000xxxxx 2 timer b3 mode register tb3mr 00??0000 2 timer b4 mode register tb4mr 00?x0000 2 timer b5 mode register tb5mr 00?x0000 2 interrupt cause select register ifsr 00 16 si/o3 transmit/receive register s3trr ?? 16 si/o4 transmit/receive register s4trr ?? 16 si/o3 control register s3c 01000000 2 si/o3 bit rate generator s3brg ? ? 16 si/o4 bit rate generator s4brg ? ? 16 si/o4 control register s4c 01000000 2 uart2 special mode register u2smr x0000000 2 uart2 receive buffer register u2rb ???????? 2 ?????xx? 2 uart2 transmit buffer register u2tb ???????? 2 xxxxxxx? 2 uart2 transmit/receive control register 0 u2c0 00001000 2 uart2 transmit/receive mode register u2mr 00 16 uart2 transmit/receive control register 1 u2c1 00000010 2 uart2 bit rate generator u2brg ?? 16 timer a4-1 register ta41 ?? 16 ?? 16 uart2 special mode register 2 u2smr2 x0000000 2 note : the blank areas are reserved and cannot be used by users. x : nothing is mapped to this bit ? : undefined uart2 special mode register 3 u2smr3 0 00x0x0x 2 interrupt cause select register 2 ifsr2a 00xxxxxx 2 uart0 special mode register 2 u0smr2 x0000000 2 uart0 special mode register u0smr x0000000 2 uart0 special mode register 3 u0smr3 0 00x0x0x 2 uart0 special mode register 4 u0smr4 0 0 16 uart1 special mode register 2 u1smr2 x0000000 2 uart1 special mode register u1smr x0000000 2 uart1 special mode register 3 u1smr3 0 00x0x0x 2 uart1 special mode register 4 u1smr4 0 0 16 uart2 special mode register 4 u2smr4 0 0 16
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r sfr 18 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. 0380 16 0381 16 0382 16 0383 16 0384 16 0385 16 0386 16 0387 16 0388 16 0389 16 038a 16 038b 16 038c 16 038d 16 038e 16 038f 16 0390 16 0391 16 0392 16 0393 16 0394 16 0395 16 0396 16 0397 16 0398 16 0399 16 039a 16 039b 16 039c 16 039d 16 039e 16 039f 16 03a0 16 03a1 16 03a2 16 03a3 16 03a4 16 03a5 16 03a6 16 03a7 16 03a8 16 03a9 16 03aa 16 03ab 16 03ac 16 03ad 16 03ae 16 03af 16 03b0 16 03b1 16 03b2 16 03b3 16 03b4 16 03b5 16 03b6 16 03b7 16 03b8 16 03b9 16 03ba 16 03bb 16 03bc 16 03bd 16 03be 16 03bf 16 timer a0 register ta0 ?? 16 ?? 16 timer a1 register ta1 ?? 16 ?? 16 timer a2 register ta2 ?? 16 ?? 16 timer b0 register tb0 ?? 16 ?? 16 timer b1 register tb1 ?? 16 ?? 16 timer b2 register tb2 ?? 16 ?? 16 count start flag tabsr 00 16 one-shot start flag onsf 00 16 timer a0 mode register ta0mr 00 16 timer a1 mode register ta1mr 00 16 timer a2 mode register ta2mr 00 16 timer b0 mode register tb0mr 0 0??0000 2 timer b1 mode register tb1mr 0 0?x0000 2 timer b2 mode register tb2mr 0 0?x0000 2 up-down flag udf 0 0 16 timer a3 register ta3 ?? 16 ?? 16 timer a4 register ta4 ?? 16 ?? 16 timer a3 mode register ta3mr 00 16 timer a4 mode register ta4mr 00 16 trigger select register trgsr 00 16 clock prescaler reset flag cpsrf 0xxxxxxx 2 uart0 transmit/receive mode register u0mr 00 16 uart0 transmit buffer register u0tb ???????? 2 xxxxxxx? 2 uart0 receive buffer register u0rb ???????? 2 ?????xx? 2 uart1 transmit/receive mode register u1mr 00 16 uart1 transmit buffer register u1tb ???????? 2 xxxxxxx? 2 uart1 receive buffer register u1rb ???????? 2 ?????xx? 2 uart0 bit rate generator u0brg ? ? 16 uart0 transmit/receive control register 0 u0c0 00001000 2 uart0 transmit/receive control register 1 u0c1 00000010 2 uart1 bit rate generator u1brg ?? 16 uart1 transmit/receive control register 0 u1c0 00001000 2 uart1 transmit/receive control register 1 u1c1 00000010 2 dma1 request cause select register dm1sl 0 0 16 dma0 request cause select register dm0sl 0 0 16 crc data register crcd ?? 16 ?? 16 crc input register crcin ? ? 16 uart transmit/receive control register 2 ucon x0000000 2 note : the blank areas are reserved and cannot be used by users. x : nothing is mapped to this bit ? : undefined timer b2 special mode register tb2sc xxxxxx00 2 address register symbol after reset
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r sfr 19 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. 03c0 16 03c1 16 03c2 16 03c3 16 03c4 16 03c5 16 03c6 16 03c7 16 03c8 16 03c9 16 03ca 16 03cb 16 03cc 16 03cd 16 03ce 16 03cf 16 03d0 16 03d1 16 03d2 16 03d3 16 03d4 16 03d5 16 03d6 16 03d7 16 03d8 16 03d9 16 03da 16 03db 16 03dc 16 03dd 16 03de 16 03df 16 03e0 16 03e1 16 03e2 16 03e3 16 03e4 16 03e5 16 03e6 16 03e7 16 03e8 16 03e9 16 03ea 16 03eb 16 03ec 16 03ed 16 03ee 16 03ef 16 03f0 16 03f1 16 03f2 16 03f3 16 03f4 16 03f5 16 03f6 16 03f7 16 03f8 16 03f9 16 03fa 16 03fb 16 03fc 16 03fd 16 03fe 16 03ff 16 note 1: the blank areas are reserved and cannot be used by users. note 2: at hardware reset 1 or hardware reset 2, the register is as follows: ? 00000000 2 where l is inputted to the cnv ss pin ? 00000010 2 where h is inputted to the cnv ss pin at software reset, watchdog timer reset and oscillation stop detection reset, the register is as follows: ? 00000000 2 where the pm01 to pm00 bits in the pm0 register are 00 2 (single-chip mode) ? 00000010 2 where the pm01 to pm00 bits in the pm0 register are 01 2 (memory expansion mode) or 11 2 (microprocessor mode) x : nothing is mapped to this bit ? : unde f ined a-d register 7 ad7 ???????? 2 xxxxxx?? 2 a-d register 0 ad0 ???????? 2 xxxxxx?? 2 a-d register 1 ad1 ???????? 2 xxxxxx?? 2 a-d register 2 ad2 ???????? 2 xxxxxx?? 2 a-d register 3 ad3 ???????? 2 xxxxxx?? 2 a-d register 4 ad4 ???????? 2 xxxxxx?? 2 a-d register 5 ad5 ???????? 2 xxxxxx?? 2 a-d register 6 ad6 ???????? 2 xxxxxx?? 2 a-d control register 0 adcon0 00000??? 2 d-a register 0 da0 ?? 16 d-a register 1 da1 ?? 16 d-a control register dacon 00 16 a-d control register 2 adcon2 00 16 a-d control register 1 adcon1 00 16 port p0 register p0 ?? 16 port p0 direction register pd0 00 16 port p1 register p1 ?? 16 port p1 direction register pd1 00 16 port p2 register p2 ?? 16 port p2 direction register pd2 00 16 port p3 register p3 ?? 16 port p3 direction register pd3 00 16 port p4 register p4 ?? 16 port p4 direction register pd4 00 16 port p5 register p 5 ?? 16 port p5 direction register pd5 00 16 port p6 register p 6 ?? 16 port p6 direction register pd6 00 16 port p7 register p 7 ?? 16 port p7 direction register pd7 00 16 port p8 register p 8 ?? 16 port p8 direction register pd8 00x00000 2 port p9 register p 9 ?? 16 port p9 direction register pd9 00 16 port p10 register p10 ?? 16 port p10 direction register pd10 00 16 pull-up control register 0 pur0 00 16 pull-up control register 1 pur1 00000000 2 00000010 2 pull-up control register 2 pur2 00 16 port control register pcr 00 16 port p14 control register pc14 xx00xxxx 2 pull-up control register 3 pur3 00 16 port p11 register p11 ?? 16 port p12 register p12 ?? 16 port p13 register p13 ?? 16 port p11 direction register pd11 00 16 port p12 direction register pd12 00 16 port p13 direction register pd13 00 16 register symbol after reset address (note 2)
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r reset 20 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. reset there are four types of resets: a hardware reset, a software reset, an watchdog timer reset, and an oscilla- tion stop detection reset. hardware reset there are two types of hardware resets: a hardware reset 1 and a hardware reset 2. hardware reset 1 ____________ ____________ a reset is applied using the reset pin. when an l signal is applied to the reset pin while the power supply voltage is within the recommended operating condition, the pins are initialized (see table 1.5.1). the oscillation circuit is initialized and the main clock starts oscillating. when the input ____________ level at the reset pin is released from l to h, the cpu and sfr are initialized, and the program is executed starting from the address indicated by the reset vector. the internal ram is not initialized. ____________ if the reset pin is pulled l while writing to the internal ram, the internal ram becomes indetermi- nate. figure 1.5.1 shows the example reset circuit. figure 1.5.2 shows the reset sequence. table 1.5.1 ____________ shows the statuses of the other pins while the reset pin is l. figure 1.5.3 shows the cpu register status after reset. refer to sfr for sfr status after reset. 1. when the power supply is stable ____________ (1) apply an l signal to the reset pin. (2) supply a clock for 20 cycles or more to the x in pin. ____________ (3) apply an h signal to the reset pin. 2. power on ____________ (1) apply an l signal to the reset pin. (2) let the power supply voltage increase until it meets the recommended operating condition. (3) wait td(p-r) or more until the internal power supply stabilizes. (4) supply a clock for 20 cycles or more to the x in pin. ____________ (5) apply an h signal to the reset pin. hardware reset 2 this reset is generated by the microcomputers internal voltage detection circuit. the voltage detec- tion circuit monitors the voltage supplied to the v cc1 pin. if the vc26 bit in the vcr2 register is set to 1 (reset level detection circuit enabled), the microcom- puter is reset when the voltage at the v cc1 input pin drops below vdet3. similarly, if the vc25 bit in the vcr2 register is set to 1 (ram retention limit detection circuit en- abled), the microcomputer is reset when the voltage at the vcc1 input pin drops below vdet2. conversely, when the input voltage at the v cc1 pin rises to vdet3 or more, the pins and the cpu and sfr are initialized, and the program is executed starting from the address indicated by the reset vector. it takes about td(s-r) before the program starts running after vdet3 is detected. the initialized pins and registers and the status thereof are the same as in hardware reset 1. set the cm10 bit in the cm1 register to 1 (stop mode) after setting the vc25 bit to 1 (ram retention limit detection circuit enabled), and the microcomputer will be reset when the voltage at the vcc1 input pin drops below vdet2 and comes out of reset when the voltage at the v cc1 input pin rises above vdet3. during stop mode, the value set in the vc26 bit has no effect. therefore, no reset is generated even when the input voltage at the v cc1 pin drops to vdet3 or less.
reset 21 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. software reset when the pm03 bit in the pm0 register is set to 1 (microcomputer reset), the microcomputer has its pins, cpu, and sfr initialized. then the program is executed starting from the address indicated by the reset vector. select the main clock for the cpu clock source, and set the pm03 bit to 1 with main clock oscillation satisfactorily stable. at software reset, some sfrs are not initialized. refer to sfr. also, since the pm01 to pm00 bits in the pm0 register are not initialized, the processor mode remains unchanged. watchdog timer reset where the pm12 bit in the pm1 register is 1 (reset when watchdog timer underflows), the microcom- puter initializes its pins, cpu and sfr if the watchdog timer underflows. then the program is executed starting from the address indicated by the reset vector. at watchdog timer reset, some sfrs are not initialized. refer to sfr. also, since the pm01 to pm00 bits in the pm0 register are not initialized, the processor mode remains unchanged. oscillation stop detection reset where the cm27 bit in the cm2 register is 0 (reset at oscillation stop detection), the microcomputer initializes its pins, cpu and sfr, coming to a halt if it detects main clock oscillation circuit stop. refer to the section oscillation stop, re-oscillation detection function. at oscillation stop detection reset, some sfrs are not initialized. refer to the section sfr. also, since the pm01 to pm00 bits in the pm0 register are not initialized, the processor mode remains unchanged. figure 1.5.1. example reset circuit reset v c c 1 r e s e t v c c 1 0 v 0 v more than 20 cycles of x in + td(p-r) are needed. e q u a l t o o r l e s s t h a n 0 . 2 v c c 1 n o t e : w h e n t h e m i c r o c o m p u t e r i s u s e d u n d e r t h e c o n d i t i o n v c c 1 v c c 2 , m a k e s u r e t h e v c c 2 v o l t a g e d o e s n o t e x c e e d t h e v c c 1 v o l t a g e w h e n p o w e r i n g u p , o r p o w e r i n g d o w n t h e m i c r o c o m p u t e r . equal to or less than 0.2v cc1 re c o m m e n d e d o p e r a t i n g v o l t a g e
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r reset 22 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.5.2. reset sequence td(p-r) more than 20 cycles are needed bclk address address address microprocessor mode byte = h microprocessor mode byte = l single chip mode x in reset rd wr cs0 rd wr cs0 content of reset vector bclk 28cycles ffffc 16 ffffd 16 ffffe 16 content of reset vector ffffc 16 ffffe 16 content of reset vector ffffe 16 ffffc 16 v cc1 , v cc2
reset 23 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. ____________ table 1.5.1. pin status when reset pin level is l status cnv ss = v cc1 cnv ss = v ss byte = v ss byte = v cc pin name p0 p1 p2, p3, p4 0 to p4 3 p4 4 p4 5 to p4 7 p5 0 p5 1 p5 2 p5 3 p5 4 p5 5 p5 6 p5 7 p6, p7, p8 0 to p8 4 , p8 6 , p8 7 , p9, p10 input port input port input port input port input port input port input port input port input port input port input port input port input port input port data input data input address output (undefined) bclk output ale output (l is output) cs0 output (h is output) wr output (h is output) rd output (h is output) rdy input input port bclk output bhe output (undefined) hlda output (the output value depends on the input to the hold pin) hold input data input address output (undefined) cs0 output (h is output) input port ( pulled high ) input port input port rdy input ale output (l is output) hold input hlda output (the output value depends on the input to the hold pin) rd output (h is output) bhe output (undefined) wr output (h is output) p11, p12, p13, p14 0 , p14 1 input port input port input port (note) note : p11, p12, p13, p14 0 , p14 1 pins exist in 128-pin version. input port ( pulled high ) figure 1.5.3. cpu register status after rreset b15 b0 data register(r0) address register(a0) frame base register(fb) program counter(pc) interrupt table register(intb) user stack pointer(usp) interrupt stack pointer(isp) static base register(sb) flag register(flg) 0000 16 0000 16 0000 16 aa aa a aa aaaaaa aa a aa aa aa cdzsboiu ipl 0000 16 0000 16 0000 16 0000 16 0000 16 b19 b0 content of addresses ffffe 16 to ffffc 16 b15 b0 b15 b0 b15 b0 b7 b8 00000 16 data register(r1) data register(r2) data register(r3) address register(a1) 0000 16 0000 16 0000 16
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r reset 24 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. voltage detection circuit the voltage detection circuit has circuits to monitor the input voltage at the v cc1 pin, each checking the input voltage with respect to vdet2, vdet3, and vdet4, respectively. use the vc25 to vc27 bits in the vcr2 register to select whether or not to enable these circuits. enable the ram retention limit detection circuit when using hardware reset 2 in stop mode, or when using the wdc5 bit in the wdc register. the wdc5 bit indicates that the ram is retained. use the reset level detection circuit for hardware reset 2. the power supply down detection circuit can be set to detect whether the input voltage is equal to or greater than vdet4 or less than vdet4 by using the vc13 bit in the vcr1 register. furthermore, a power supply down detection interrupt can be used. figure 1.5.4. reset circuit block b 7 b 6 b 5 v c r 2 r e g i s t e r r e s e t cm10 bit=1 (stop mode) + e v d e t 2 + vdet3 + v d e t 4 e n o i s e r e j e c t i o n power supply down detection signal b3 vcr1 register vc13 bit internal power on reset w r i t e t o w d c r e g i s t e r s r q w a r m / c o l d >t q 1 s h o t t d ( s - r ) internal reset signal (l active) wdc5 bit i n t e r n a l p o w e r s u p p l y v o l t a g e s t a b l e t i m e e (cold start, warm start) v c c 1 t d q h a l f l a t c h figure 1.5.5. wdc register watchdog timer control register symbol address a fter reset wdc 000f 16 00xxxxxx 2 (note2) function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 high-order bit of watchdog timer wdc7 bit name prescaler select bit 0 : divided by 16 1 : divided by 128 reserved bit s et to 0 0 ro rw rw rw cold start / warm start discrimination flag (note 1) 0 : cold start 1 : warm start wdc5 note 1: the wdc5 bit is always 1 (= warm start) no matter how it is set by writing a 0 or 1. note 2: the wdc5 bit is 0 (= cold start) immediately after power-on. it can only be set to 1 in a program. it is set to 0 when the input voltage at the v cc1 pin drops to v det 2 or less while the vcr2 registers vc25 bit = 1 (ram retention limit detection circuit enabled). (b4-b0) (b6)
reset 25 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.5.6. vcr1 register, vcr2 register, and d4int register vc13 power supply detection register 1 symbol address a fter reset (note 2) vcr1 0019 16 00001000 2 power supply down monitor flag (note 1) bit name function bit symbol rw b7 b 6 b 5 b4 b 3 b 2 b1 b 0 note 1: the vc13 bit is useful when the vc27 bit of vcr2 register is set to 1 (power supply down detection circuit enable). the vc13 bit is always 1 (v cc1 4 v) when the vc27 bit in the vcr2 register is set to 0 (power supply down detection circuit disable). note 2: this register does not change at software reset, watchdog timer reset and oscillation stop detection reset. 0:v cc1 < vdet4 1:v cc1 vdet4 ro 0 0 0 0 0 0 0 rw rw reserved bit reserved bit must set to 0 must set to 0 power supply detection register 2 (note 1) symbol address a fter reset (note 6) vcr2 001a 16 00 16 bit name bit symbol b7 b 6 b 5 b4 b 3 b 2 b1 b 0 note 1: write to this register after setting the prc3 bit in the prcr register to 1 (write enable). note 2: to use hardware reset 2, set the vc26 bit to 1 (reset level detection circuit enable). note 3: to use hardware reset 2 in stop mode, set the vc25 bit to 1 (ram retention limit detection circuit enable). vc26 bit is disabled in stop mode. (the microcomputer is not reset even if the voltage input to vcc 1 pin becomes lower than vdet3.) note 4: to use the wdc5 bit in the wdc register, set the vc25 bit to 1 (ram retention limit detection circuit enable). note 5: where the vc13 bit in the vcr1 register and d42 bit in the d4int register are used or the d40 bit is set to 1 (power supply down detection interrupt enable), set the vc27 bit to 1 (power supply down detection circuit enable). note 6: this register does not change at software reset, watchdog timer reset and oscillation stop detection reset. note 7: the detection circuit does not start operation until td(e-a) elapses after the vc25 bit, vc26 bit, or vc27 bit is set to 1 . vc25 ram retention limit detection monitor bit (notes 3, 4, 7) 0: disable ram retention limit detection circuit 1: enable ram retention limit detection circuit vc26 vc27 rw rw rw rw rw 0 0 0 0 0 function reserved bit must set to 0 reset level monitor bit (notes 2, 3, 7) 0: disable reset level detection circuit 1: enable reset level detection circuit power supply down monitor bit (note 5) 0: disable power supply down detection circuit 1: enable power supply down detection circuit (b2-b0) (b7-b4) (b4-b0) d40 power supply down detection interrupt register (note 1) symbol address after reset d4int 001f 16 00 16 power supply down detection interrupt enable bit (note 5) bit name bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 : disable 1 : enable d41 stop mode deactivation control bit (note 4) 0: disable (do not use the power supply down detection interrupt to get out of stop mode) 1: enable (use the power supply down detection interrupt to get out of stop mode) d42 power supply change detection flag (note 2) 0: not detected 1: vdet4 passing detection d43 wdt overflow detect flag 0: not detected 1: detected df0 sampling clock select bit 00 : cpu clock divided by 8 01 : cpu clock divided by 16 10 : cpu clock divided by 32 11 : cpu clock divided by 64 df1 note 1: write to this register after setting the prc3 bit in the prcr register to 1 (write enable). note 2: useful when the vc27 bit in the vcr2 register is set to 1 (power supply down detection circuit enabled). if the vc27 bit is set to 0 (power supply down detection circuit disable), the d42 bit is set to 0 (not detect). note 3: this bit is set to 0 by writing a 0 in a program. (writing a 1 has no effect.) note 4: if the power supply down detection interrupt needs to be used to get out of stop mode again after once used for that purpose, reset the d41 bit by writing a 0 and then a 1. note 5: the d40 bit is useful where the vc27 bit in the vcr2 register is set to 1. b5 b4 rw rw rw rw (note 3) rw rw rw (b7-b6) function (note 3) nothing is assigned. when write, set to 0. when read, its content is 0.
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r reset 26 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.5.7. typical operation of hardware reset 2 vdet4 vdet3 5.0v 5.0v v cc1 internal reset signal vc13 bit vc26 bit vc27 bit set to 1 in a program (reset level detection circuit enable) set to 1 in a program (power supply down detection circuit enable) typical operation 1 of hardware reset 2 5.0v 5.0v v cc1 wdc5 bit vc13 bit vc25 bit vc27 bit set to 1 in a program (warm start) set to 1 in a program (ram retention limit detection circuit enable) set to 1 in a program (power supply down detection circuit enable) typical operation 2 of hardware reset 2 internal reset signal cm10 bit set to 1 in a program (stop mode) v ss undefined undefined undefined undefined undefined undefined undefined undefined reset vdet4 vdet3s v ss vdet2 reset vdet3s vdet3r vdet3r
reset 27 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. power supply down detection interrupt a power supply down detection interrupt request is generated when the input voltage at the v cc1 pin rises to vdet4 or more or drops below vdet4 while the d40 bit in the d4int register is set to 1 (power supply down detection interrupt enable). the power supply down detection interrupt shares the interrupt vector with the watchdog timer interrupt and oscillation stop, re-oscillation detection interrupt. to use the power supply down detection interrupt to get out of stop mode, set the d41 bit in the d4int register to 1 (enable). the d42 bit in the d4int register becomes 1 when passing through vdet4 is detected after the voltage inputted to the v cc1 pin is up or down. a power supply down detection interrupt is generated when the d42 bit changes state from 0 to 1. the d42 bit needs to be set to 0 in a program. however, where the d41 bit is 1 and the stop mode is selected, the power supply down detection interrupt request arises, and the microcomputer is reset from the stop mode with no regard for the status of d42 bit if it is detected that the voltage applied to the v cc1 pin has increased, passing through vdet4. table 1.5.2 shows the power supply down detection interrupt request generation conditions. it is possible to set the sampling clock detecting that the voltage applied to the v cc1 pin has passed through vdet4 with the df1 to df0 bits of d4int register. table 1.5.3 shows sampling clock periods. table 1.5.2. power supply down detection interrupt request generation conditions bit, vdet4 passing detection, operation mode condition vc27 bit generated from 1 to 1 (no change) not detected note 1: the status except the wait mode and stop mode is handled as the normal mode.(refer to clock generating circuit) note 2: refer to limitations on stop mode, limitations on wait mode. d40 bit vdet4 passing detection d42 bit d41 bit vc13 bit operation mode (notes 1, 2) power supply down detection interrupt request 0 not generated 1 0 1 detected from 0 to 1 0 normal, wait stop not generated 1 generated 0 not generated 1 from 0 to 1 (up) normal, wait stop generated from 1 to 0 (down) not generated table 1.5.3. sampling clock periods cpu clock (mhz) divided by 8 divided by 16 divided by 32 divided by 64 sampling clock (s) 16 1.5 3.0 6.0 12.0 precautions 1. limitations on stop mode if the cm10 bit in the cm1 register is set to 1 (stop mode) when the vc13 bit in the vcr1 register is 1 (v cc1 vdet4) while the vc27 bit in the vcr2 register is 1 (power supply down detection circuit enable) and the d40 bit in the d4int register is 1 (power supply down detection interrupt enable) and d41 bit in the d4int register is 1 (power supply down detection interrupt is used to get out of stop mode), a power supply down detection interrupt is immediately generated, causing the microcomputer to exit stop mode. in systems where the microcomputer enters stop mode when the input voltage at the v cc1 pin drops below vdet4 and exits stop mode when the input voltage rises to vdet4 or more, make sure the cm10 bit is set to 1 when vc13 bit is 0 (v cc1 < vdet4).
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r reset 28 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. 2. limitations on wait instruction if the wait instruction is executed when the vc13 bit in the vcr1 register is 1 (v cc1 vdet4) while the vc27 bit in the vcr2 register is 1 (power supply down detection circuit enable) and the d40 bit in the d4int register is 1 (power supply down detection interrupt enable), a power supply down detection interrupt is immediately generated, causing the microcomputer to exit wait mode. in systems where the microcomputer enters wait mode when the input voltage at the v cc1 pin drops below vdet4 and exits wait mode when the input voltage rises to vdet4 or more, make sure the wait instruction is executed when vc13 bit is 0 (v cc1 < vdet4). figure 1.5.8. power supply down detection interrupt generation block power supply down detection interrupt generation circuit oscillation stop, re-oscillation detection interrupt signal watchdog timer block this bit is set to 0(not detected) by writing a 0 in a program. d43 d41 cm02 wait instruction(wait mode) d40 vc27 v cc1 v ref + - (rejection wide:200 ns) vc13 h when vc27 bit= 0 (disabled) noise rejection circuit digital filter bclk d42 df1, df0 1/2 00 2 01 2 10 2 11 2 1/2 1/2 1/8 noise rejection power supply down detection signal watchdog timer underflow signal d42 bit is set to 0(not detected) by writing a 0 in a program. vc27 bit is set to 0 (power supply down detection circuit disabled), the d42 bit is set to 0. power supply down detection circuit power supply down detection interrupt signal watchdog timer interrupt signal non-maskable interrupt signal figure 1.5.9. power supply down detection interrupt generation circuit operation example output of the digital filter (note 2) d42 bit note 1 : d40 is 1(power supply down detection interrupt enabled) note 2 : output of the digital filter shown in figure 1.5.8. power supply down detection interrupt signal no power supply down detection interrupt signals are generated when the d42 bit is h. sampling set to 0 in a program (not detected) vc13 bit v cc1 sampling sampling sampling set to 0 in a program (not detected)
29 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r processor mode under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. processor mode (1) types of processor mode three processor modes are available to choose from: single-chip mode, memory expansion mode, and microprocessor mode. table 1.6.1 shows the features of these processor modes. (2) setting processor modes processor mode is set by using the cnv ss pin and the pm01 to pm00 bits in the pm0 register. table 1.6.2 shows the processor mode after hardware reset. table 1.6.3 shows the pm01 to pm00 bit set values and processor modes. table 1.6.2. processor mode after hardware reset table 1.6.1. features of processor modes processor modes access space p ins which are assigned i/o ports single-chip mode sfr, internal ram, internal rom all pins are i/o ports or peripheral function i/o pins memory expansion mode sfr, internal ram, internal rom, external area (note) some pins serve as bus control pins (note) microprocessor mode sfr, internal ram, external area (note) some pins serve as bus control pins (note) note : refer to bus. cnv ss pin input level processor mode v ss single-chip mode v cc1 (note 1, note 2) microprocessor mode note 1: if the microcomputer is reset in hardware by applying v cc1 to the cnv ss pin (hardware reset 1 or hardware reset 2), the internal rom cannot be accessed regardless of pm10 to pm00 bits. note 2: the multiplexed bus cannot be assigned to the entire cs space. table 1.6.3. pm01 to pm00 bits set values and processor modes pm01 to pm00 bits processor modes single-chip mode memory expansion mode must not be set 00 2 01 2 10 2 microprocessor mode 11 2 rewriting the pm01 to pm00 bits places the microcomputer in the corresponding processor mode regard- less of whether the input level on the cnv ss pin is h or l. note, however, that the pm01 to pm00 bits cannot be rewritten to 01 2 (memory expansion mode) or 11 2 (microprocessor mode) at the same time the pm07 to pm02 bits are rewritten. note also that these bits cannot be rewritten to enter microprocessor mode in the internal rom, nor can they be rewritten to exit microprocessor mode in areas overlapping the internal rom. if the microcomputer is reset in hardware by applying v cc1 to the cnv ss pin (hardware reset 1 or hard- ware reset 2), the internal rom cannot be accessed regardless of pm01 to pm00 bits. figures 1.6.1 and 1.6.2 show the registers associated with processor modes. figure 1.6.3 show the memory map in single chip mode.
30 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r processor mode under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.6.1. pm0 register processor mode register 0 (note 1) symbol address a fter reset (note 4) pm0 0004 16 00000000 2 ( cnv ss pin = l ) 00000011 2 ( cnv ss pin = h ) bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 0 0: single-chip mode 0 1: memory expansion mode 1 0: must not be set 1 1: microprocessor mode b1 b0 pm03 pm01 pm00 processor mode bit (note 4) pm02 r/w mode select bit 0 : rd,bhe,wr 1 : rd,wrh,wrl software reset bit setting this bit to 1 resets the microcomputer. when read, its content is 0. pm04 0 0 : multiplexed bus is unused (separate bus in the entire cs space) 0 1 : allocated to cs2 space 1 0 : allocated to cs1 space 1 1 : allocated to the entire cs space (note 3) b5 b4 multiplexed bus space select bit pm05 rw rw rw rw pm06 pm07 port p4 0 to p4 3 function select bit (note 2) 0 : address output 1 : port function (address is not output) bclk output disable bit 0 : bclk is output 1 : bclk is not output (pin is left high-impedance) note 1: write to this register after setting the prc1 bit in the prcr register to "1" (write enable). note 2: effective when the pm01 to pm00 bits are set to 01 2 (memory expansion mode) or 11 2 (microprocessor mode). note 3: to set the pm01 to pm00 bits are 01 2 and the pm05 to pm04 bits are 11 2 (multiplexed bus assigned to the entire cs space), apply an h signal to the byte pin (external data bus is 8 bits wide). while the cnv ss pin is held h (= v cc1 ), do not rewrite the pm05 to pm04 bits to 11 2 after reset. if the pm05 to pm04 bits are set to 11 2 during memory expansion mode, p3 1 to p3 7 and p4 0 to p4 3 become i/o ports, in which case the accessible area for each cs is 256 bytes. note 4: the pm01 to pm00 bits do not change at software reset, watchdog timer reset and oscillation stop detection reset. rw rw rw rw (note 2) (note 2) (note 2)
31 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r processor mode under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.6.2. pm1 register processor mode register 1 (note 1) symbol address after reset pm1 0005 16 0x001000 2 bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 cs2 area switch bit (data block enable bit) 0: 08000 16 to 26fff 16 (block a disable) 1: 10000 16 to 26fff 16 (block a enable) pm10 (note 2) rw port p3 7 to p3 4 function select bit note 1: write to this register after setting the prc1 bit in the prcr register to 1 (write enable). note 2: for the mask rom version, this bit must be set to 0 . for the flash memory version, the pm10 bit also controls block a by enabling or disabling it. however, the pm10 bit is automatically set to 1 when the fmr01 bit in the fmr0 register is 1 (cpu rewrite mode). note 3: effective when the pm01 to pm00 bits are set to 01 2 (memory expansion mode) or 11 2 (microprocessor mode). note 4: pm12 bit is set to 1 by writing a 1 in a program. (writing a 0 has no effect.) note 5: when pm17 bit is set to 1 (with wait state), one wait state is inserted when accessing the internal ram, internal rom, or an external area. if the csiw bit (i = 0 to 3) in the csr register is 0 (with wait state), the csi area is always accessed with one or more wait states regardless of whether the pm17 bit is set or not. where the rdy signal is used or multiplex bus is used, set the csiw bit to 0 (with wait state). note 6: the access area is changed by the pm13 bit as listed in the table below. pm17 wait bit (note 5) 0 : no wait state 1 : with wait state (1 wait) internal reserved area expansion bit pm13 see note 6 should be set to 0. 0 : watchdog timer interrupt 1 : watchdog timer reset (note 4) watchdog timer function select bit pm12 pm14 pm15 memory area expansion bit (note 3) 0 0 : 1 mbyte mode (do not expand) 0 1 : must not be set 1 0 : must not be set 1 1 : 4 mbyte mode b5 b4 pm11 (note 3) 0 : address output 1 : port function rw rw rw rw rw rw (b6) access area internal ram rom up to addresses 00400 16 to 03fff 16 (15 kbytes) up to addresses d0000 16 to fffff 16 (192 kbytes) pm13=0 pm13=1 the entire area is usable the entire area is usable external addresses 04000 16 to 07fff 16 are usable addresses 80000 16 to cffff 16 are usable addresses 04000 16 to 07fff 16 are reserved addresses 80000 16 to cffff 16 are reserved reserved bit rw 0
32 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r processor mode under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. single-chip mode sfr internal ram can not use internal rom 00000 16 00400 16 xxxxx 16 yyyyy 16 fffff 16 note 1: for the mask rom version, set the pm10 bit to 0 (08000 16 to 26fff 16 for cs2 area). note 2: if pm13 bit is set to 0, 15 kbytes of the internal ram and 192 kbytes of the internal rom can be used. pm13=0 pm13=1 capacity address yyyyy16 128k bytes e0000 16 256k bytes d0000 16 (note 2) capacity address xxxxx 16 12k bytes 033ff 16 20k bytes 03fff 16 (note 2) 10k bytes 02bff 16 24k bytes 03fff 16 (note 2) 384k bytes d0000 16 (note 2) 512k bytes d0000 16 (note 2) internal ram internal rom 4k bytes 013ff 16 5k bytes 017ff 16 31k bytes 03fff 16 (note 2) 48k bytes f4000 16 64k bytes f0000 16 96k bytes e8000 16 192k bytes d0000 16 320k bytes d0000 16 (note 2) 128k bytes e0000 16 256k bytes c0000 16 12k bytes 033ff 16 20k bytes 053ff 16 10k bytes 02bff 16 24k bytes 063ff 16 384k bytes a0000 16 512k bytes 80000 16 internal ram internal rom 4k bytes 013ff 16 5k bytes 017ff 16 31k bytes 07fff 16 48k bytes f4000 16 64k bytes f0000 16 96k bytes e8000 16 192k bytes d0000 16 320k bytes b0000 16 16k bytes 043ff 16 16k bytes 03fff 16 (note 2) capacity capacity address yyyyy 16 address xxxxx 16 figure 1.6.3. memory map in single chip mode
bus 33 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. bus during memory expansion or microprocessor mode, some pins serve as the bus control pins to perform _______ data input/output to and from external devices. these bus control pins include a 0 to a 19 , d 0 to d 15 , cs0 _______ _____ ________ ______ ________ ________ ________ __________ _________ to cs3, rd, wrl/wr, wrh/bhe, ale, rdy, hold, hlda and bclk. bus mode the bus mode, either multiplexed or separate, can be selected using the pm05 to pm04 bits. separate bus in this bus mode, data and address are separate. multiplexed bus in this bus mode, data and address are multiplexed. if the data bus is 8 bits wide, d 0 to d 7 and a 0 to a 7 are multiplexed. if the data bus is 16 bits wide, d 0 to d 7 and a 1 to a 8 are multiplexed, with d 8 to d 15 not multiplexed. in this case, external devices connecting to the multiplexed bus are mapped to the even addresses of the microcomputer.
bus 34 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. function bit symbol bit name chip select control register symbol address after reset csr 0008 16 00000001 2 rw b7 b6 b5 b4 b3 b2 b1 b0 cs1 cs0 cs3 cs2 cs0 output enable bit cs1 output enable bit cs2 output enable bit cs3 output enable bit cs1w cs0w cs3w cs2w cs0 wait bit cs1 wait bit cs2 wait bit cs3 wait bit 0 : chip select output disabled (functions as i/o port) 1 : chip select output enabled 0 : with wait state 1 : without wait state rw rw rw rw rw rw rw rw (note 1, note 2, note 3) note 1: where the rdy signal is used in the area indicated by csi (i = 0 to 3) or the multiplex bus is used, set the csiw bit to 0 (wait state). note 2: if the pm17 bit in the pm1 register is set to 1 (with wait state), the external area indicated by cs0 to cs3 is always accessed with one wait state even when the csiw bit is 1 (without wait state). note 3: when the csiw bit = 0 (with wait state), the number of wait states (interms of clock cycles) can be selected using the csei1w to csei0w bits in the cse register. figure 1.7.1. csr register bus control the following describes the signals needed for accessing external devices and the functionality of software wait. (1) address bus the address bus consists of 20 lines, a 0 to a 19 . the address bus width can be chosen to be 12, 16 or 20 bits by using the pm06 bit in the pm0 register and the pm11 bit in the pm1 register. table 1.7.1 shows the pm06 and pm11 bit set values and address bus widths. when processor mode is changed from single-chip mode to memory extension mode, the address bus is indeterminate until any external area is accessed. (2) data bus when input on the byte pin is high, 8 lines d 0 to d 7 comprise the data bus; when input on the byte pin is low, 16 lines d 0 to d 15 comprise the data bus. do not change the input level on the byte pin while in operation. (3) chip select signal ______ ______ the chip select (hereafter referred to as the csi) signals are output from the csi (i = 0 to 3) pins. _____ these pins can be chosen to function as i/o ports or as cs by using the csi bit in the csr register. figure 1.7.1 shows the csr register. ______ during 1 mbyte mode, the external area can be separated into up to 4 by the csi signal which is output ______ ______ ______ from the csi pin. during 4 mbyte mode, csi signal or bank number is output from the csi pin. refer to ______ memory space expansion function. figure 1.7.2 shows the example of address bus and csi signal output in 1 mbyte mode. set value(note) pin function pm11=1 p3 4 to p3 7 address bus wide 12 bits pm06=1 p4 0 to p43 pm11=0 a 12 to a15 16 bits pm06=1 p4 0 to p43 pm11=0 a 12 to a15 20 bits pm06=0 a 16 to a19 note 1: no values other than those shown above can be set. table 1.7.1. pm06 and pm11 bits set value and address bus width
bus 35 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. ______ figure 1.7.2. example of address bus and csi signal output in 1 mbyte mode example 1 bclk read signal data bus address bus csi access to the external area indicated by csi access to the external area indicated by csj address data csj data bclk read signal data bus address bus csi access to the external area indicated by csi access to the internal rom or internal ram address data bclk read signal data bus address bus csi access to the external area indicated by csi access to the same external area address data data bclk read signal data bus address bus csi access to the external area indicated by csi no access address data address address shown above is the case where separate bus is selected and the area is accessed for read without wait states. i = 0 to 3, j = 0 to 3 (not including i, however) to access the external area indicated by csj in the next cycle after accessing the external area indicated by csi the address bus and the chip select signal both change state between these two cycles. example 2 to access the internal rom or internal ram in the next cycle after accessing the external area indicated by csi the chip select signal changes state but the address bus does not change state example 4 not to access any area (nor instruction prefetch generated) in the next cycle after accessing the external area indicated by csi neither the address bus nor the chip select signal changes state between these two cycles example 3 to access the external area indicated by csi in the next cycle after accessing the external area indicated by the same csi the address bus changes state but the chip select signal does not change state note : these examples show the address bus and chip select signal when accessing areas in two successive cycles. the chip selec t bus cycle may be extended more than two cycles depending on a combination of these examples.
bus 36 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. _____ ______ ________ table 1.7.3. operation of rd, wr and bhe signals status of external data bus rd bhe wr hll lhl hlh lhh write 1 byte of data to an odd address read 1 byte of data from an odd address write 1 byte of data to an even address read 1 byte of data from an even address data bus width a0 h h l l hll l lhl l hl h or l lh h or l 8-bit (byte pin input = h) write data to both even and odd addresses read data from both even and odd addresses write 1 byte of data read 1 byte of data 16-bit (byte pin input = l) (note) (note) note : do not use. status of external data bus read data write 1 byte of data to an even address write 1 byte of data to an odd address write data to both even and odd addresses wrh wrl rd data bus width 16-bit ( byte pin input = l) h h h h l h l h h l l l _____ ________ _________ table 1.7.2. operation of rd, wrl and wrh signals (4) read and write signals _____ when the data bus is 16 bits wide, the read and write signals can be chosen to be a combination of rd, ________ ______ _____ ________ ________ bhe and wr or a combination of rd, wrl and wrh by using the pm02 bit in the pm0 register. when _____ ______ ________ the data bus is 8 bits wide, use a combination of rd, wr and bhe. _____ ________ _________ table 1.7.2 shows the operation of rd, wrl, and wrh signals. table 1.7.3 shows the operation of _____ ______ ________ operation of rd, wr, and bhe signals. (5) ale signal the ale signal latches the address when accessing the multiplex bus space. latch the address when the ale signal falls. when byte pin input = h when byte pin input = l ale address data address (note) a 0 /d 0 to a 7 /d 7 a 8 to a 19 ale address data address a 1 /d 0 to a 8 /d 7 a 9 to a 19 address a 0 note : if the entire cs space is assigned a multiplexed bus, these pins function as i/o ports. figure 1.7.3. ale signal, address bus, data bus
bus 37 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. ________ figure 1.7.4. example in which wait state was inserted into read cycle by rdy signal bclk rd cs i (i=0 to 3) rdy tsu(rdy - bclk) aaaa bclk rd cs i (i=0 to 3) rdy tsu(rdy - bclk) aaaaaa aa aa in an instance of separate bus in an instance of multiplexed bus accept timing of rdy signal : wait using rdy signal : wait using software accept timing of rdy signal shown above is the case where cseiw to csei1w (i = 0 to 3) bits are 00 2 (one wait state). ________ (6) the rdy signal this signal is provided for accessing external devices which need to be accessed at low speed. if input on ________ the rdy pin is asserted low at the last falling edge of bclk of the bus cycle, one wait state is inserted in ________ the bus cycle. while in a wait state, the following signals retain the state in which they were when the rdy signal was acknowledged. ______ ______ ______ ________ ________ ______ ________ __________ a 0 to a 19 , d 0 to d 15 , cs0 to cs3, rd, wrl, wrh, wr, bhe, ale, hlda ________ then, when the input on the rdy pin is detected high at the falling edge of bclk, the remaining bus cycle is executed. figure 1.7.4 shows example in which the wait state was inserted into the read cycle by the ________ ________ rdy signal. to use the rdy signal, set the corresponding bit (cs3w to cs0w bits) in the csr register ________ ________ to 0 (with wait state). when not using the rdy signal, process the rdy pin as an unused pin.
bus 38 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. table 1.7.4. microcomputer status in hold state item status bclk output _______ _______ _____ ________ _________ _______ _______ a 0 to a 19 , d 0 to d 15 , cs0 to cs3, rd, wrl, wrh, wr, bhe high-impedance i/o ports p0, p1, p3, p4(note 2) high-impedance p6 to p14(note 1) m aintains status when hold signal is received __________ hlda output l internal peripheral circuits on (but watchdog timer stops) ale signal undefined __________ hold > dmac > cpu (7) hold signal this signal is used to transfer control of the bus from the cpu or dma to an external circuit. when input __________ on the hold pin is asserted l, the microcomputer goes to a hold state after completing the bus access __________ then in progress. while the hold pin is held l, the microcomputer remains in a hold state, outputting a __________ low signal from the hlda pin. table 1.7.4 shows the microcomputer status in the hold state. __________ bus-using priorities are given to hold, dmac, and cpu in order of decreasing precedence. figure 1.7.5. bus-using priorities note 1: p11 to p14 are included in the 128-pin version. note 2: when i/o port function is selected. (8) bclk output if the pm07 bit in the pm0 register is set to 0 (output enable), a clock with the same frequency as that of the cpu clock is output as bclk from the bclk pin. refer to cpu clock and pheripheral clock.
bus 39 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. processor mode memory expansion mode or microprocessor mode memory expansion mode 00 2 (separate bus) pm05Cpm04 bits 01 2 (cs2 is for multiplexed bus and others are for separate bus) 10 2 (cs1 is for multiplexed bus and others are for separate bus) data bus width 8 bits h byte pin p0 0 to p0 7 d 0 to d 7 d 0 to d 7 d 0 to d 7 d 0 to d 7 i/o ports p1 0 to p1 7 i/o ports d 8 to d 15 i/o ports d 8 to d 15 i/o ports p2 0 a 0 a 0 a 0 /d 0 (note 2) a 0 a 0 /d 0 p2 1 to p2 7 a 1 to a 7 a 1 to a 7 a 1 to a 7 /d 1 to d 7 (note 2) a 1 to a 7 /d 0 to d 6 (note 2) a 1 to a 7 /d 1 to d 7 p3 0 a 8 a 8 a 8 a 8 /d 7 (note 2) a 8 p3 1 to p3 3 a 9 to a 11 i/o ports p3 4 to p3 7 a 12 to a 15 i/o ports p4 0 to p4 3 a 16 to a 19 i/o ports p4 4 i/o ports p4 5 p4 6 p4 7 p5 0 wrl p5 2 rd p5 3 bclk p5 4 hlda p5 5 hold p5 6 ale p5 7 rdy 11 2 (multiplexed bus for the entire space) (note 1) pm11=0 pm11=1 i/o ports pm06=0 pm06=1 i/o ports cs0=0 cs0=1 cs0 i/o ports cs1=0 cs1=1 cs1 i/o ports cs2=0 cs2=1 cs2 i/o ports cs3=0 cs3=1 cs3 pm02=0 pm02=1 wr (note 3) wrl (note 3) (note 3) p5 1 bhe wrh pm02=0 pm02=1 (note 3) wrh (note 3) (note 3) note 1: to set the pm01 to pm00 bits are set to 01 2 and the pm05 to pm04 bits are set to 11 2 (multiplexed bus assigned to the entire cs space), apply h to the byte pin (external data bus 8 bits wide). while the cnv ss pin is held h (= v cc1 ), do not rewrite the pm05 to pm04 bits to 11 2 after reset. if the pm05 to pm04 bits are set to 11 2 during memory expansion mode, p3 1 to p3 7 and p4 0 to p4 3 become i/o ports, in which case the accessible area for each cs is 256 bytes. note 2: in separate bus mode, these pins serve as the address bus. note 3: if the data bus is 8 bits wide, make sure the pm02 bit is set to 0 (rd, bhe, wr). i/o ports: function as i/o ports or peripheral function i/o pins. 8 bits h 8 bits h 16 bits l 16 bits l table 1.7.5. pin functions for each processor mode
bus 40 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. (10) software wait software wait states can be inserted by using the pm17 bit in the pm1 register, the cs0w to cs3w bits in the csr register, and the cse register. ________ to use the rdy signal, set the corresponding cs3w to cs0w bit to 0. figure 1.7.6 shows the cse register. table 1.7.7 shows the software wait related bits and bus cycles. figure 1.7.7 and 1.7.8 show the typical bus timings using software wait. (9) external bus status when internal area accessed table 1.7.6 shows the external bus status when the internal area is accessed. table 1.7.6. external bus status when internal area accessed item sfr accessed internal rom, ram accessed a 0 to a 19 address output maintain status before accessed address of external area or sfr d 0 to d 15 when read high-impedance high-impedance when write output data undefined rd, wr, wrl, wrh rd, wr, wrl, wrh output output h bhe bhe output maintain status before accessed status of external area or sfr cs0 to cs3 output h output h ale output l output l figure 1.7.6. cse register function bit symbol bit name chip select expansion control register symbol address after reset cse 001b 16 00 16 rw b7 b6 b5 b4 b3 b2 b1 b0 cse00w cs0 wait expansion bit 0 0: 1 wait 0 1: 2 waits 1 0: 3 waits 1 1: must not be set b1 b0 cse01w (note) cse10w cs1 wait expansion bit 0 0: 1 wait 0 1: 2 waits 1 0: 3 waits 1 1: must not be set b3 b2 cse11w (note) cse20w cs2 wait expansion bit 0 0: 1 wait 0 1: 2 waits 1 0: 3 waits 1 1: must not be set b5 b4 cse21w (note) cse30w cs3 wait expansion bit 0 0: 1 wait 0 1: 2 waits 1 0: 3 waits 1 1: must not be set b7 b6 cse31w (note) note: set the csiw bit (i = 0 to 3) in the csr register to 0 (with wait state) before writing to the csei1w to csei0w bits. if the csiw bit needs to be set to 1 (without wait state), set the csei1w to csei0w bits to 00 2 before setting it. rw rw rw rw rw rw rw rw
bus 41 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. bus mode pm1 register pm17 bit cse register cse31w to cse30w bit cse21w to cse20w bit cse11w to cse10w bit cse01w to cse00w bit bus cycle separate bus multiplexed bus (note 2) note 1: to use the rdy signal, set this bit to 0. note 2: to access in multiplexed bus mode, set the corresponding bit of cs0w to cs3w to 0 (with wait state). note 3: after reset, the pm17 bit is set to 0 (without wait state), all of the cs0w to cs3w bits are set to 0 (with wait state), and the cse register is set to 00 16 (one wait state for cs0 to cs3). therefore, the internal ram and internal rom are accessed with no wait states, and all exter nal areas are accessed with one wait state. 0 1 0 1 1 1 0 0 0 1 0 0 0 0 00 2 00 2 01 2 10 2 00 2 01 2 10 2 1 bclk cycle (note 3) 2 bclk cycles 1 bclk cycle (read) 2 bclk cycles (write) 2 bclk cycles (note 3) 3 bclk cycles 4 bclk cycles 2 bclk cycles 3 bclk cycles 3 bclk cycles 4 bclk cycles 3 bclk cycles csr register cs3w bit (note 1) cs2w bit (note 1) cs1w bit (note 1) cs0w bit (note 1) internal ram, rom external area area software wait no wait 1 wait no wait 1 wait 2 waits 3 waits 1 wait 1 wait 2 waits 3 waits 1 wait 00 2 00 2 table 1.7.7. bit and bus cycle related to software wait
bus 42 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.7.7. typical bus timings using software wait (1) bclk read signal write signal data bus address bus address address output input address address bus cycle (note) bus cycle (note) (1) separate bus, no wait setting (2) separate bus, 1-wait setting output input note : these example timing charts indicate bus cycle length. after this bus cycle sometimes come read and write cycles in succession. bus cycle (note) bus cycle (note) (3) separate bus, 2-wait setting output address address bus cycle (note) bus cycle (note) input bclk bclk cs read signal write signal data bus address bus cs cs read signal write signal data bus address bus
bus 43 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.7.8. typical bus timings using software wait (2) address address data output address address input bus cycle (note) bus cycle (note) (1) separate bus, 3-wait setting read signal write signal address bus/ data bus cs address bus ale (3)multiplexed bus, 3-wait setting output note : these example timing charts indicate bus cycle length. after this bus cycle sometimes come read and write cycles in succession. bus cycle (note) bus cycle (note) input address address address bus/ data bus address address data output address address input ale bus cycle (note) (2)multiplexed bus, 1- or 2-wait setting bus cycle (note) bclk cs bclk cs bclk write signal read signal data bus address bus write signal read signal address bus
44 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r memory space expansion function under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. memory space expansion function the following describes a memory space extension function. during memory expansion or microprocessor mode, the memory space expansion function allows the access space to be expanded using the appropriate register bits. table 1.8.1 shows the way of setting memory space expansion function, memory spaces. table 1.8.1. the way of setting memory space expansion function, memory space memory space expansion function how to set (pm15 to pm14) memory space 1 mbytes mode 00 2 1 mbytes (no expansion) 4 mbytes mode 11 2 4 mbytes (1) 1 mbyte mode in this mode, the memory space is 1 mbytes. in 1 mbyte mode, the external area to be accessed is ______ ______ specified using the csi (i = 0 to 3) signals (hereafter referred to as the csi area). figures 1.8.2 to 1.8.3 _____ show the memory mapping and cs area in 1 mbyte mode. (2) 4 mbyte mode in this mode, the memory space is 4 mbytes. figure 1.8.1 shows the dbr register. the bsr2 to bsr0 bits select a bank number which is to be accessed to read or write data. setting the ofs bit to 1 (with offset) allows the accessed address to be offset by 40000 16 . ______ in 4 mbyte mode, the csi (i=0 to 3) pin functions differently for each area to be accessed. addresses 04000 16 to 3ffff 16 , c0000 16 to fffff 16 ______ ______ ? the csi signal is output from the csi pin (same operation as 1 mbyte mode. however the last address _______ of cs1 area is 3ffff 16 ) addresses 40000 16 to bffff 16 ______ ? the cs0 pin outputs l ______ ______ ? the cs1 to cs3 pins output the value of the bsr2 to bsr0 bits (bank number) ______ figures 1.8.4 to 1.8.5 show the memory mapping and cs area in 4 mbyte mode. note that banks 0 to 6 ______ are data-only areas. locate the program in bank 7 or the csi area. figure 1.8.1. dbr register data bank register (note) symbol address a fter reset dbr 0 00b 16 00 16 bit name description bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 ofs offset bit 0: not offset 1: offset bsr0 bank selection bits 0 0 0: bank 0 0 0 1: bank 1 0 1 0: bank 2 0 1 1: bank 3 1 0 0: bank 4 1 0 1: bank 5 1 1 0: bank 6 1 1 1: bank 7 nothing is assigned. when write, set to 0. when read, its content is 0. nothing is assigned. when write, set to 0. when read, its content is 0. b5 b4 b3 b5 b4 b3 rw rw bsr1 bsr2 (b1-b0) (b7-b6) rw rw note : effective when the pm01 to pm00 bits are set to 01 2 (memory expansion mode) or 11 2 (microprocessor mode).
45 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r memory space expansion function under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. aaaaa aaaaa aaaaa aaaaa aaaaa aaaaa microprocessor mode 00000 16 00400 16 xxxxx 16 yyyyy 16 fffff 16 80000 16 08000 16 memory expansion mode sfr internal ram internal rom reserved area reserved, external area cs2 (pm10=0: 124 kbytes) cs1 (32 kbytes) cs0 (microprocessor mode:832 kbytes) 28000 16 30000 16 reserved area 27000 16 capacity address yyyyy 16 128 kbytes e0000 16 256 kbytes c0000 16 capacity address xxxxx 16 12 kbytes 033ff 16 20 kbytes 053ff 16 10 kbytes 02bff 16 24 kbytes 063ff 16 384 kbytes a0000 16 512 kbytes 80000 16 pm13=1 external area 10000 16 aaaaa aaaaa aaaaa aaaaa aaaaa aaaaa aaaaa aaaaa sfr internal ram reserved area reserved area external area cs2 (pm10=1: 92 kbytes) cs0 (memory expansion mode:320 kbytes ) internal ram internal rom cs0 memory expansion mode 30000 16 e7ffff 16 external area cs1 microprocessor mode 30000 16 efffff 16 28000 16 e 2ffff 16 cs2 when pm10=0 08000 16 e26fff 16 when pm10=1 10000 16 e26fff 16 cs3 no area 4 kbytes 013ff 16 5 kbytes 017ff 16 31 kbytes 07fff 16 48 kbytes f4000 16 64 kbytes f0000 16 96 kbytes e8000 16 192 kbytes d0000 16 320 kbytes b0000 16 16 kbytes 043ff 16 reserved, external area aaaa aaaa aaaa aaaa aaaa aaaa microprocessor mode 00000 16 00400 16 xxxxx 16 yyyyy 16 fffff 16 d0000 16 08000 16 memory expansion mode aaaa aaaa sfr internal ram internal rom reserved area reserved area cs3 (16 kbytes) cs2 (pm10=0: 124 kbytes) cs1 (32 kbytes) cs0 (microprocessor mode:832 kbytes) 28000 16 30000 16 04000 16 reserved area 27000 16 capacity address yyyyy 16 128 kbytes e0000 16 256 kbytes d0000 16 (note) capacity address xxxxx 16 12 kbytes 033ff 16 20 kbytes 03fff 16 (note) 10 kbytes 02bff 16 24 kbytes 03fff 16 (note) 384 kbytes d0000 16 (note) 512 kbytes d0000 16 (note) pm13=0 reserved, external area external area 10000 16 aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa sfr internal ram reserved area reserved area reserved, external area external area cs2 (pm10=1: 92 kbytes) cs0 (memory expansion mode:640 kbytes ) internal ram internal rom cs0 memory expansion mode 30000 16 ecffff 16 external area cs1 microprocessor mode 30000 16 efffff 16 28000 16 e 2ffff 16 cs2 when pm10=0 08000 16 e26fff 16 when pm10=1 10000 16 e26fff 16 cs3 04000 16 e 07fff 16 4 kbytes 013ff 16 5 kbytes 017ff 16 31 kbytes 03fff 16 (note) 48 kbytes f4000 16 64 kbytes f0000 16 96 kbytes e8000 16 192 kbytes d0000 16 320 kbytes d0000 16 (note) 16 kbytes 03fff 16 (note) note : if pm13 bit is set to 0, 15 kbytes of the internal ram and 192 kbytes of the internal rom can be used. ______ figure 1.8.2. memory mapping and cs area in 1 mbyte mode (pm13=0) ______ figure 1.8.3. memory mapping and cs area in 1 mbyte mode (pm13=1)
46 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r memory space expansion function under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. ______ figure 1.8.4. memory mapping and cs area in 4 mbyte mode (pm13=0) aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa microprocessor mode 00000 16 00400 16 xxxxx 16 yyyyy 16 fffff 16 d0000 16 08000 16 memory expansion mode aaaaaa aaaaaa sfr internal ram internal rom reserved area reserved area cs3 (16 kbytes) cs2 (pm10=0: 124 kbytes) cs1 (96 kbytes) cs0 (microprocessor mode:256 kbytes) 28000 16 40000 16 04000 16 reserved area 27000 16 pm13=0 reserved, external area external area 10000 16 aaaaa aaaaa aaaaa aaaaa aaaaa aaaaa aaaaa aaaaa aaaaa aaaaa sfr internal ram reserved area reserved area external area cs2 (pm10=1: 92 kbytes) cs0 (memory expansion mode:64 kbytes ) cs0 memory expansion mode c0000 16 ecffff 16 external area cs1 microprocessor mode c0000 16 efffff 16 28000 16 e 3ffff 16 cs2 when pm10=0 08000 16 e26fff 16 when pm10=1 10000 16 e26fff 16 cs3 04000 16 e 07fff 16 c0000 16 other than the cs area (512 kbytes x 8 banks) 40000 16 ebffff 16 other than the cs area (note 1) note 1: the cs0 pin outputs a low signal, and the cs1ecs3 pins output a bank number. note 2: if pm13 bit is set to 0, 15 kbytes of the internal ram and 192 kbytes of the internal rom can be used. capacity address yyyyy 16 128 kbytes e0000 16 256 kbytes d0000 16 (note2) capacity address xxxxx 16 12 kbytes 033ff 16 20 kbytes 03fff 16 (note2) 10 kbytes 02bff 16 24 kbytes 03fff 16 (note2) 384 kbytes d0000 16 (note2) 512 kbytes d0000 16 (note2) internal ram internal rom 4 kbytes 013ff 16 5 kbytes 017ff 16 31 kbytes 03fff 16 (note2) 48 kbytes f4000 16 64 kbytes f0000 16 96 kbytes e8000 16 192 kbytes d0000 16 320 kbytes d0000 16 (note2) 16 kbytes 03fff 16 (note2) reserved, external area aaaaa aaaaa aaaaa aaaaa aaaaa microprocessor mode 00000 16 00400 16 xxxxx 16 yyyyy 16 fffff 16 c0000 16 08000 16 memory expansion mode sfr internal ram internal rom reserved area reserved area cs2 (pm10=0: 124 kbytes) cs1 (96 kbytes) cs0 (microprocessor mode:256 kbytes) 28000 16 40000 16 reserved area 27000 16 pm13=1 external area 10000 16 aaaaa aaaaa aaaaa aaaaa aaaaa aaaaa aaaaa aaaaa sfr internal ram reserved area reserved area external area cs2 (pm10=1: 92 kbytes) other than the cs area (microprocessor mode:512 kbytes x 8 banks) cs0 external area cs1 microprocessor mode c0000 16 efffff 16 28000 16 e 3ffff 16 cs2 when pm10=0 08000 16 e26fff 16 when pm10=1 10000 16 e26fff 16 cs3 no area 80000 16 other than the cs area (memory expansion mode:256 kbytes x 8 banks)* *two 256 kbytes x 8 banks can be used by changing the offset. other than the cs area (note) memory expansion mode 04000 16 e7ffff 16 microprocessor mode 04000 16 ebffff 16 note : the cs0 pin outputs a low signal, and the cs1ecs3 pins output a bank number. capacity address yyyyy 16 128 kbytes e0000 16 256 kbytes c0000 16 capacity address xxxxx 16 12 kbytes 033ff 16 20 kbytes 053ff 16 10 kbytes 02bff 16 24 kbytes 063ff 16 384 kbytes a0000 16 512 kbytes 80000 16 internal ram internal rom 4 kbytes 013ff 16 5 kbytes 017ff 16 31 kbytes 07fff 16 48 kbytes f4000 16 64 kbytes f0000 16 96 kbytes e8000 16 192 kbytes d0000 16 320 kbytes b0000 16 16 kbytes 043ff 16 reserved, external area reserved, external area ______ figure 1.8.5. memory mapping and cs area in 4 mbyte mode (pm13=1)
47 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r memory space expansion function under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.8.6 shows the external memory connect example in 4 mbyte mode. _____ _______ in this example, the cs pin of 4-mbyte rom is connected to the cs0 pin of microcomputer. the address _______ _______ _______ input ad21, ad20 and ad19 pins are connected to the cs3, cs2 and cs1 pins of microcomputer, respectively. the address input ad18 pin is connected to the a19 pin of microcomputer. figures 1.8.7 to 1.8.9 show the relationship of addresses between the 4-mbyte rom and the microcomputer for the case of a connection example in figure 1.8.6. in microprocessor mode, or in memory expansion mode where the pm13 bit is 0, banks are located every 512 kbytes. setting the ofs bit to 1 allows the accessed address to be offset by 40000 16 , so that even the data overlapping a bank boundary can be accessed in succession. in memory expansion mode where the pm13 bit is 1, each 512-kbyte bank can be accessed in 256 kbyte units by switching them over with the ofs bit. ____ _______ because the sram can be accessed on condition that the chip select signals s2 = h and s1 =l, cs0 _______ _____ ____ and cs2 can be connected to s2 and s1, respectively. if the sram does not have the input pins to accept _______ _______ h active and l active chip select signals, cs0 and cs2 should be decoded external to the chip. 17 8 microcomputer d0 to d7 a0 to a16 a17 rd wr cs1 cs2 cs3 cs0 a19 4m bytes rom dq0 to dq7 ad0 to ad16 ad17 ad18 ad19 oe cs 128k bytes sram dq0 to dq7 ad0 to ad16 s2 w oe s1 ad20 ad21 note: if only one chip select pin (s1 or s2) is present, decoding by use of an external circuit is required. (note) figure 1.8.6. external memory connect example in 4m byte mode
48 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r memory space expansion function under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. 000000 16 080000 16 100000 16 180000 16 200000 16 280000 16 380000 16 3fffff 16 rom address microcomputer address 40000 16 bffff 16 3c0000 16 340000 16 2c0000 16 240000 16 1c0000 16 140000 16 0c0000 16 040000 16 bank 0 bank 1 bank 1 bank 2 bank 2 bank 3 bank 3 bank 4 bank 4 bank 5 bank 5 bank 6 bank 6 bank 7 aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa data program or data ofs bit of the dbr register=0 ofs bit of the dbr register=1 300000 16 bank 0 40000 16 40000 16 40000 16 40000 16 40000 16 40000 16 40000 16 bffff 16 bffff 16 bffff 16 bffff 16 bffff 16 bffff 16 40000 16 bffff 16 40000 16 bffff 16 40000 16 bffff 16 40000 16 bffff 16 40000 16 bffff 16 40000 16 bffff 16 40000 16 bffff 16 program or data bffff 16 figure 1.8.7. relationship between addresses on 4-m byte rom and those on microcomputer (1) a20 a19 a18 n.c. a17 a16 a15Ca0 address input for 4-mbyte rom address input for 4- mbyte rom a 18 cs output address output ofs access area output from the microcomputer pins cs3 c s2 cs1 a 19 a 17 a 16 a 15 Ca 0 40000 16 0 0000 16 000000 16 bank number 0 0 bffff 16 ffff 16 040000 16 1 080000 16 1 0 0c0000 16 1 100000 16 2 0 140000 16 1 180000 16 3 0 1c0000 16 1 200000 16 4 0 240000 16 1 280000 16 5 0 2c0000 16 1 300000 16 6 0 340000 16 1 40000 16 380000 16 7 0 80000 16 3c0000 16 c0000 16 3c0000 16 d0000 16 internal rom access internal rom access internal rom access internal rom access a21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 1 1 1 1 0 0 1 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 40000 16 bffff 16 40000 16 bffff 16 40000 16 bffff 16 40000 16 bffff 16 40000 16 bffff 16 40000 16 bffff 16 40000 16 bffff 16 40000 16 bffff 16 40000 16 bffff 16 40000 16 bffff 16 40000 16 bffff 16 40000 16 bffff 16 40000 16 bffff 16 7ffff 16 bffff 16 cffff 16 dffff 16 d0000 16 dffff 16 0000 16 ffff 16 0000 16 ffff 16 0000 16 ffff 16 0000 16 ffff 16 0000 16 ffff 16 0000 16 ffff 16 0000 16 ffff 16 0000 16 ffff 16 0000 16 ffff 16 0000 16 ffff 16 0000 16 ffff 16 0000 16 ffff 16 0000 16 ffff 16 0000 16 ffff 16 0000 16 ffff 16 0000 16 ffff 16 07ffff 16 0bffff 16 0fffff 16 13ffff 16 17ffff 16 1bffff 16 1fffff 16 23ffff 16 27ffff 16 2bffff 16 2fffff 16 33ffff 16 37ffff 16 3bffff 16 3bffff 16 3fffff 16 3cffff 16 n.c.: no connected memory expansion mode where pm13 =0
49 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r memory space expansion function under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.8.8. relationship between addresses on 4-m byte rom and those on microcomputer (2) 000000 16 080000 16 100000 16 180000 16 200000 16 280000 16 380000 16 3fffff 16 rom address 40000 16 7ffff 16 3c0000 16 340000 16 2c0000 16 240000 16 1c0000 16 140000 16 0c0000 16 040000 16 bank 0 bank 1 bank 1 bank 2 bank 2 bank 3 bank 3 bank 4 bank 4 bank 5 bank 5 bank 6 bank 6 bank 7 aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa data program or data 300000 16 bank 0 microcomputer address ofs bit of the dbr register=0 ofs bit of the dbr register=1 40000 16 7ffff 16 40000 16 7ffff 16 40000 16 7ffff 16 40000 16 7ffff 16 40000 16 7ffff 16 40000 16 7ffff 16 40000 16 7ffff 16 40000 16 7ffff 16 40000 16 7ffff 16 40000 16 7ffff 16 40000 16 7ffff 16 40000 16 7ffff 16 40000 16 7ffff 16 40000 16 7ffff 16 program or data bank 7 40000 16 7ffff 16 a20 a19 a18 n.c. a17 a16 a15Ca0 address input for 4-mbyte rom address input for 4- mbyte rom a 18 cs output address output ofs access area output from the microcomputer pins cs3 c s2 cs1 a 19 a 17 a 16 a 15 Ca 0 7ffff 16 0 0000 16 000000 16 bank number 0 0 07ffff 16 1 080000 16 1 0 0c0000 16 1 100000 16 2 0 140000 16 1 180000 16 3 0 1c0000 16 1 200000 16 4 0 240000 16 1 280000 16 5 0 2c0000 16 1 300000 16 6 0 1 1 340000 16 1 0 0 380000 16 7 0 internal rom access 71 1 1 3c0000 16 80000 16 internal rom access internal rom access internal rom access a21 03ffff 16 040000 16 0bffff 16 0fffff 16 13ffff 16 17ffff 16 1bffff 16 1fffff 16 23ffff 16 27ffff 16 2bffff 16 2fffff 16 33ffff 16 37ffff 16 3bffff 16 3fffff 16 ffff 16 0000 16 ffff 16 0000 16 ffff 16 0000 16 ffff 16 0000 16 ffff 16 0000 16 ffff 16 0000 16 ffff 16 0000 16 ffff 16 0000 16 ffff 16 0000 16 ffff 16 0000 16 ffff 16 0000 16 ffff 16 0000 16 ffff 16 0000 16 ffff 16 0000 16 ffff 16 0000 16 ffff 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 40000 16 7ffff 16 40000 16 7ffff 16 40000 16 7ffff 16 40000 16 7ffff 16 40000 16 7ffff 16 40000 16 7ffff 16 40000 16 7ffff 16 40000 16 7ffff 16 40000 16 7ffff 16 40000 16 7ffff 16 40000 16 7ffff 16 40000 16 7ffff 16 40000 16 7ffff 16 40000 16 7ffff 16 40000 16 fffff 16 80000 16 7ffff 16 40000 16 fffff 16 n.c.: no connected memory expansion mode where pm13 =1
50 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r memory space expansion function under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.8.9. relationship between addresses on 4-m byte rom and those on microcomputer (3) 000000 16 080000 16 100000 16 180000 16 200000 16 280000 16 380000 16 3fffff 16 rom address microcomputer address 40000 16 bffff 16 3c0000 16 340000 16 2c0000 16 240000 16 1c0000 16 140000 16 0c0000 16 040000 16 bank 0 bank 1 bank 1 bank 2 bank 2 bank 3 bank 3 bank 4 bank 4 bank 5 bank 5 bank 6 bank 6 bank 7 aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa data program or data ofs bit of the dbr register=0 ofs bit of the dbr register=1 300000 16 bank 0 40000 16 40000 16 40000 16 40000 16 40000 16 40000 16 40000 16 bffff 16 bffff 16 bffff 16 bffff 16 bffff 16 bffff 16 40000 16 bffff 16 40000 16 bffff 16 40000 16 bffff 16 40000 16 bffff 16 40000 16 bffff 16 40000 16 bffff 16 40000 16 bffff 16 program or data fffff 16 7ffff 16 c0000 16 a20 a19 a18 n.c. a17 a16 a15Ca0 address input for 4-mbyte rom address input for 4- mbyte rom a 18 cs output address output ofs access area output from the microcomputer pins cs3 c s2 cs1 a 19 a 17 a 16 a 15 Ca 0 40000 16 0 0000 16 000000 16 bank number 0 0 040000 16 1 080000 16 1 0 0c0000 16 1 100000 16 2 0 140000 16 1 180000 16 3 0 1c0000 16 1 200000 16 4 0 240000 16 1 280000 16 5 0 2c0000 16 1 300000 16 6 0 340000 16 1 380000 16 7 0 80000 16 3c0000 16 c0000 16 3c0000 16 a21 bffff 16 40000 16 bffff 16 40000 16 bffff 16 40000 16 bffff 16 40000 16 bffff 16 40000 16 bffff 16 40000 16 bffff 16 40000 16 bffff 16 40000 16 bffff 16 40000 16 bffff 16 40000 16 bffff 16 40000 16 bffff 16 40000 16 bffff 16 40000 16 bffff 16 40000 16 7ffff 16 bffff 16 fffff 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ffff 16 0000 16 ffff 16 0000 16 ffff 16 0000 16 ffff 16 0000 16 ffff 16 0000 16 ffff 16 0000 16 ffff 16 0000 16 ffff 16 0000 16 ffff 16 0000 16 ffff 16 0000 16 ffff 16 0000 16 ffff 16 0000 16 ffff 16 0000 16 ffff 16 0000 16 ffff 16 0000 16 ffff 16 0000 16 ffff 16 07ffff 16 0bffff 16 0fffff 16 13ffff 16 17ffff 16 1bffff 16 1fffff 16 23ffff 16 27ffff 16 2bffff 16 2fffff 16 33ffff 16 37ffff 16 3bffff 16 3bffff 16 3fffff 16 3fffff 16 n.c.: no connected microprocessor mode
clock generation circuit 51 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. ? cpu clock source ? peripheral function clock source use of clock main clock oscillation circuit sub clock oscillation circuit item ?cpu clock source ? timer a, b's clock source clock frequency 0 to 16 mhz 3 2.768 khz ? ceramic oscillator ? crystal oscillator usable oscillator ? crystal oscillator x in , x out pins to connect oscillator x cin , x cout presence oscillation stop, restart function presence oscillating oscillator status after reset stopped externally derived clock can be input other pll frequency synthesizer 10 to 24 mhz presence stopped ring oscillator ? cpu clock source ? peripheral function clock source ? cpu and peripheral function clock sources when the main clock stops oscillating about 1 mhz presence stopped ? cpu clock source ? peripheral function clock source clock generation circuit the clock generation circuit contains four oscillator circuits as follows: (1) main clock oscillation circuit (2) sub clock oscillation circuit (3) ring oscillator (oscillation stop detect function) (4) pll frequency synthesizer table 1.9.1 lists the clock generation circuit specifications. figure 1.9.1 shows the clock generation circuit. figures 1.9.2 to 1.9.6 show the clock-related registers. table 1.9.1. clock generation circuit specifications
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r clock generation circuit 52 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. f c32 cm02, cm04, cm05, cm06, cm07: cm0 register bits cm10, cm11, cm16, cm17: cm1 register bits pclk0, pclk1: pclk register bits cm21, cm27 : cm2 register bits 1/32 main clock generating circuit f c cm02 cm04 cm10=1(stop mode) q s r wait instruction cm05 qs r nmi interrupt request level judgment output reset software reset f c cpu clock cm07 = 0 cm07 = 1 aaa aaa divider a d 1/2 1/2 1/2 1/2 cm06=0 cm17ecm16=00 2 cm06=0 cm17ecm16=01 2 cm06=0 cm17ecm16=10 2 cm06=1 cm06=0 cm17ecm16=11 2 d a details of divider sub-clock generating circuit x cin x cout x out x in f 8 f 32 c b b 1/2 c f 32sio f 8sio f ad f 1 e e 1/2 1/4 1/8 1/16 1/32 pclk0=1 a a a a a a a pll frequency synthesizer 0 1 cm21=1 cm11 cm21=0 aaaa aaaa ring oscillator a aa aa a pll clock sub-clock ring oscillator clock bclk pclk0=0 f 2 f 1sio pclk1=1 aa a a aa pclk1=0 f 2sio main clock clk out a a a a a a pm01epm00=00 2 , cm01ecm00=01 2 pm01epm00=00 2 , cm01ecm00=10 2 cm01ecm00=00 2 i/o ports pm01epm00=00 2 , cm01ecm00=11 2 cm21 oscillation stop, re- oscillation detection circuit figure 1.9.1. clock generation circuit phase comparator charge pump voltage control oscillator (vco) pll clock main clock 1/2 programmable counter internal low- pass filter pll frequency synthesizer pulse generation circuit for clock edge detection and charge, discharge control charge, discharge circuit reset generating circuit oscillation stop, re-oscillation detection interrupt generating circuit main clock oscillation stop detection reset cm27 0 1 cm21 switch signal oscillation stop, re-oscillation detection signal oscillation stop, re-oscillation detection circuit
clock generation circuit 53 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. system clock control register 0 (note 1) symbol address a fter reset cm0 0006 16 01001000 2 bit name functionbit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0 : i/o port p5 7 0 1 : f c output 1 0 : f 8 output 1 1 : f 32 output b1 b0 cm07 cm05 cm04 cm03 cm01 cm02 cm00 cm06 clock output function select bit (valid only in single-chip mode) wait peripheral function clock stop bit (note 10) 0 : do not stop peripheral function clock in wait mode 1 : stop peripheral function clock in wait mode (note 8) x cin -x cout drive capacity select bit (note 2) 0 : low 1 : high port x c select bit 0 : i/o port p8 6 , p8 7 1 : x cin -x cout generation function(note 9) main clock stop bit (notes 3, 10, 12, 13) 0 : on 1 : off (note 4, note5) main clock division select bit 0 (notes 7, 13) 0 : cm16 and cm17 valid 1 : division by 8 mode system clock select bit (notes 6, 10, 11, 12) 0 : main clock, pll clock, or ring oscillator clock 1 : sub-clock note 1: write to this register after setting the prc0 bit of prcr register to 1 (write enable). note 2: the cm03 bit is set to 1 (high) when the cm04 bit is set to 0 (i/o port) or the microcomputer goes to a stop mode. note 3: this bit is provided to stop the main clock when the low power dissipation mode or ring oscillator low power dissipatio n mode is selected. this bit cannot be used for detection as to whether the main clock stopped or not. to stop the main clock, the following setting is required: (1) set the cm07 bit to 1 (sub-clock select) or the cm21 bit of cm2 register to 1 (ring oscillator select) with the sub-clo ck stably oscillating. (2) set the cm20 bit of cm2 register to 0 (oscillation stop, re-oscillation detection function disabled). (3) set the cm05 bit to 1 (stop). note 4: during external clock input, only the clock oscillation buffer is turned off and clock input is accepted. note 5: when cm05 bit is set to 1, the x out pin goes h. furthermore, because the internal feedback resistor remains connected, the x in pin is pulled h to the same level as x out via the feedback resistor. note 6: after setting the cm04 bit to 1 (x cin -x cout oscillator function), wait until the sub-clock oscillates stably before switching the cm07 bit from 0 to 1 (sub-clock). note 7: when entering stop mode from high or middle speed mode, ring oscillator mode or ring oscillator low power mode, the cm0 6 bit is set to 1 (divide-by-8 mode). note 8: the f c32 clock does not stop. during low speed or low power dissipation mode, do not set this bit to 1 (peripheral clock turned off when in wait mode). note 9: to use a sub-clock, set this bit to 1. also make sure ports p8 6 and p8 7 are directed for input, with no pull-ups. note 10: when the pm21 bit of pm2 register is set to 1 (clock modification disable), writing to the cm02, cm05, and cm07 bits has no effect. note 11: if the pm21 bit needs to be set to 1, set the cm07 bit to 0(main clock) before setting it. note 12: to use the main clock as the clock source for the cpu clock, follow the procedure below. (1) set the cm05 bit to 0 (oscillate). (2) wait until td(m-l) elapses or the main clock oscillation stabilizes, whichever is longer. (3) set the cm11, cm21 and cm07 bits all to 0. note 13: if the cm05 bit is set to 1 (main clock turned off) in low speed mode, the cm06 bit is set to 1 (divide-by-8 mode) and the cm15 bit is set to 1 (drive capability high). avoid changing the cm06 bit in low power dissipation mode. during ring oscillator mode, the cm06 and cm15 bits do not change even if the cm05 bit is set to 1. during ring oscillator low power dissipation mode, the divide-by-n value can be selected using the cm06 and cm17 to cm16 bits. to return to high or middle speed mode, however, set the cm06 bit to 1 and the cm15 bit to 1 before selecting the desired mode. rw (note 2) rw rw rw rw rw rw rw rw figure 1.9.2. cm0 register
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r clock generation circuit 54 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. system clock control register 1 (note 1) symbol address a fter reset cm1 0 007 16 00100000 2 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 cm10 all clock stop control bit (notes 4, 6) 0 : clock on 1 : all clocks off (stop mode) note 1: write to this register after setting the prc0 bit of prcr register to 1 (write enable). note 2: when entering stop mode from high or middle speed mode, or when the cm05 bit is set to 1 (main clock turned off) in l ow speed mode, the cm15 bit is set to 1 (drive capability high). note 3: effective when the cm06 bit is 0 (cm16 and cm17 bits enable). note 4: if the cm10 bit is 1 (stop mode), x out goes h and the internal feedback resistor is disconnected. the x cin and x cout pins are placed in the high-impedance state. when the cm11 bit is set to 1 (pll clock), or the cm20 bit of cm2 register is set to 1 (oscillation stop, re-oscillation detection function enabled), do not set the cm10 bit to 1. note 5: after setting the plc07 bit in plc0 register to 1 (pll operation), wait until tsu (pll) elapses before setting the cm11 bit to 1 (pll clock). note 6: when the pm21 bit of pm2 register is set to 1 (clock modification disable), writing to the cm10, cm011 bits has no ef fect. when the pm22 bit of pm2 register is set to 1 (watchdog timer count source is ring oscillator clock), writing to the cm10 bit has no effect. note 7: effective when cm07 bit is 0 and cm21 bit is 0 . cm15 x in -x out drive capacity select bit (note 2) 0 : low 1 : high rw cm16 cm17 reserved bit must set to 0 main clock division select bit 1 (note 3) 0 0 : no division mode 0 1 : division by 2 mode 1 0 : division by 4 mode 1 1 : division by 16 mode b7 b6 0 00 cm11 system clock select bit 1 (notes 6, 7) 0 : main clock 1 : pll clock (note 5) rw rw rw rw rw rw (b4-b2) figure 1.9.3. cm1 register
clock generation circuit 55 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. b7 b6 b5 b4 b3 b2 b1 b0 rw cm20 cm21 oscillation stop detection register (note 1) symbol address after reset cm2 000c 16 0x000000 2 (note 11) bit name function bit symbol system clock select bit 2 (notes 2, 3, 6, 8, 11) 0: oscillation stop, re-oscillation detection function disabled 1: oscillation stop, re-oscillation detection function enabled 0: main clock or pll clock (ring oscillator turned off) 1: ring oscillator clock (ring oscillator oscillating) oscillation stop, re- oscillation detection bit (notes 7, 9, 10, 11) note 1: write to this register after setting the prc0 bit of prcr register to 1 (write enable). note 2: when the cm20 bit is 1 (oscillation stop, re-oscillation detection function enabled), the cm27 bit is 1 (oscillation stop, re-oscillation detection interrupt), and the cpu clock source is the main clock, the cm21 bit is set to 1 (ring oscillator clock) if the main clock stop is detected. note 3: if the cm20 bit is 1 and the cm23 bit is 1 (main clock turned off), do not set the cm21 bit to 0. note 4: this bit becomes 1 at main clock stop detection and main clock re-oscillation detection. when this bit changes from 0 to 1, there arise oscillation stop, re-oscillation detection interrupt. use this register to discriminate the causes for oscillation stop, re-oscillation detection interrupt and watchdog timer interrupt in the interrupt processing program. by writing 0 in the program, this bit becomes 0. (even when 1 is written in the program, no change is identified for the bit. also, this bit is not set to 0 where there occur oscillation stop, re-oscillation detection interrupt.) when the cm22 bit is 1, no oscillation stop, re- oscillation detection interrupt occur even if oscillation stop or re-oscillation is detected. note 5: read the cm23 bit in an oscillation stop, re-oscillation detection interrupt handling routine to determine the main clock status. note 6: effective when the cm07 bit of cm0 register is 0. note 7: when the pm21 bit of pm2 register is 1 (clock modification disabled), writing to the cm20 bit has no effect. note 8: where the cm20 bit is 1 (oscillation stop, re-oscillation detection function enabled), the cm27 bit is 1 (oscillation stop, re-oscillation detection interrupt), and the cm11 bit is 0 (the cpu clock source is pll clock), the cm21 bit remains unchanged even when main clock stop is detected. if the cm22 bit is 0 under these conditions, oscillation stop, re-oscillation detection interrupt occur at main clock stop detection; it is, therefore, necessary to set the cm21 bit to 1 (ring oscillator clock) inside the interrupt routine. note 9: set the cm20 bit to 0 (disable) before entering stop mode. after exiting stop mode, set the cm20 bit back to 1 (enable). note 10: set the cm20 bit to 0 (disable) before setting the cm05 bit of cm0 register. note 11: the cm20, cm21 and cm27 bits do not change at oscillation stop detection reset. cm22 cm23 oscillation stop, re- oscillation detection flag 0: main clock stop, re-oscillation not detected 1: main clock stop, re-oscillation detected 0: main clock oscillating 1: main clock turned off x in monitor flag (note 4) cm27 0: oscillation stop detection reset 1: oscillation stop, re-oscillation detection interrupt nothing is assigned. when write, set to 0. when read, its content is indeterminate. operation select bit (when an oscillation stop, re-oscillation is detected) (note 11) rw rw rw rw ro (b6) (note 5) reserved bit (b5-b4) must set to 0 rw 00 figure 1.9.4. cm2 register
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r clock generation circuit 56 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.9.5. pclkr register and pm2 register function bit symbol bit name peripheral clock select register (note) symbol address when reset pclkr 025e 16 00000011 2 rw b7 b6 b5 b4 b3 b2 b1 b0 pclk0 timers a, b clock select bit (clock source for the timers a, b, and the dead time timer) 0 : f 2 1 : f 1 000 reserved bit must set to 0 note: write to this register after setting the prc0 bit of prcr register to 1 (write enable). 000 pclk1 si/o clock select bit (clock source for uart0 to uart2, si/o3, si/o4) 0 : f 2sio 1 : f 1sio rw rw rw (b7-b2) function bit symbol bit name processor mode register 2 (note 1) symbol address after reset pm2 001e 16 xxx00000 2 rw b7 b6 b5 b4 b3 b2 b1 b0 pm20 specifying wait when accessing sfr at pll operation 0 : 2 waits 1 : 1 wait 00 reserved bit must set to 0 nothing is assigned. when write, set to 0. when read, its content is interdeterminate. note 1: write to this register after setting the prc1 bit of prcr register to 1 (write enable). note 2: this bit can only be rewritten while the plc07 bit is 0 (pll turned off). also, to select a 16 mhz or higher pll clock, set this bit to 0 (2 waits). note that if the clock source for the cpu clock is to be changed from the pll clock to another, the plc07 bit must be set to 0 before setting the pm20 bit. note 3: once this bit is set to 1, it cannot be cleared to 0 in a program. note 4: setting the pm21 bit to 1 results in the following conditions: ? the bclk is not halted by executing the wait instruction. ? writing to the following bits has no effect. cm02 bit of cm0 register cm05 bit of cm0 register (main clock is not halted) cm07 bit of cm0 register (cpu clock source does not change) cm10 bit of cm1 register (stop mode is not entered) cm11 bit of cm1 register (cpu clock source does not change) cm20 bit of cm2 register (oscillation stop, re-oscillation detection function settings do not change) all bits of plc0 register (pll frequency synthesizer settings do not change) note 5: setting the pm22 bit to 1 results in the following conditions: ? the ring oscillator starts oscillating, and the ring oscillator clock becomes the watchdog timer count source. ? the cm10 bit of cm1 register is disabled against write. (writing a 1 has no effect, nor is stop mode entered.) ? the watchdog timer does not stop when in wait mode or hold state. (note 2) rw rw rw pm21 (b7-b5) system clock protective bit 0 : clock is protected by prcr register 1 : clock modification disabled pm22 wdt count source protective bit (note 3, note 4) (note 3, note 5) 0 : cpu clock is used for the watchdog timer count source 1 : ring oscillator clock is used for the watchdog timer count source rw (b4-b3)
clock generation circuit 57 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.9.6. plc0 register plc00 plc01 plc02 plc07 (note 3) (note 4) function note 1: write to this register after setting the prc0 bit of prcr register to 1 (write enable). note 2: when the pm21 bit of pm2 register is 1 (clock modification disable), writing to this register has no effect. note 3: these three bits can only be modified when the plc07 bit = 0 (pll turned off). the value once written to this bit cannot be modified. note 4: before setting this bit to 1 , set the cm07 bit to 0 (main clock), set the cm17 to cm16 bits to 00 2 (main clock undivided mode), and set the cm06 bit to 0 (cm16 and cm17 bits enable). pll control register 0 (note 1, note 2) pll multiplying factor select bit nothing is assigned. when write, set to 0. when read, its content is indeterminate. reserved bit operation enable bit 0 0 0: 0 0 1: multiply by 2 0 1 0: multiply by 4 0 1 1: multiply by 6 1 0 0: multiply by 8 1 0 1: 1 1 0: 1 1 1: 0: pll off 1: pll on must set to 1 bit name bit symbol symbol address after reset plc0 001c 16 0001 x010 2 rw b1b0b2 reserved bit must set to 0 do not set rw rw rw rw rw rw do not set (b4) (b6-b5) (b3) b7 b6 b5 b4 b3 b2 b1 b0 0 1 0
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r clock generation circuit 58 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. microcomputer (built-in feedback resistor) x in x out externally derived clock open vcc vss microcomputer (built-in feedback resistor) x in x out r d c in c out (note) note: insert a damping resistor if required. the resistance will vary depending on the oscillator and the oscillation drive capacity setting. use the value recommended by the maker of the oscillator. when the oscillation drive capacity is set to low, check that oscillation is stable. also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between x in and x out following the instruction. figure 1.9.7. examples of main clock connection circuit the following describes the clocks generated by the clock generation circuit. (1) main clock this clock is used as the clock source for the cpu and peripheral function clocks. this clock is used as the clock source for the cpu and peripheral function clocks. the main clock oscillator circuit is configured by connecting a resonator between the x in and x out pins. the main clock oscillator circuit contains a feedback resistor, which is disconnected from the oscillator circuit during stop mode in order to reduce the amount of power consumed in the chip. the main clock oscillator circuit may also be configured by feeding an externally generated clock to the x in pin. figure 1.9.7 shows the examples of main clock connection circuit. after reset, the main clock divided by 8 is selected for the cpu clock. the power consumption in the chip can be reduced by setting the cm05 bit of cm0 register to 1 (main clock oscillator circuit turned off) after switching the clock source for the cpu clock to a sub clock or ring oscillator clock. in this case, x out goes h. furthermore, because the internal feedback resistor remains on, x in is pulled h to x out via the feedback resistor. note that if an externally generated clock is fed into the x in pin, the main clock cannot be turned off by setting the cm05 bit to 1. if necessary, use an external circuit to turn off the clock. during stop mode, all clocks including the main clock are turned off. refer to power control.
clock generation circuit 59 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. microcomputer (built-in feedback resistor) x cin x cout externally derived clock open vcc vss note: insert a damping resistor if required. the resistance will vary depending on the oscillator and the oscillation drive capacity setting. use the value recommended by the maker of the oscillator. when the oscillation drive capacity is set to low, check that oscillation is stable. also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between x cin and x cout following the instruction. microcomputer (built-in feedback resistor) x cin x cout (note) c cin c cout r cd figure 1.9.8. examples of sub clock connection circuit (2) sub clock the sub clock is generated by the sub clock oscillation circuit. this clock is used as the clock source for the cpu clock, as well as the timer a and timer b count sources. in addition, an fc clock with the same frequency as that of the sub clock can be output from the clk out pin. the sub clock oscillator circuit is configured by connecting a crystal resonator between the x cin and x cout pins. the sub clock oscillator circuit contains a feedback resistor, which is disconnected from the oscillator circuit during stop mode in order to reduce the amount of power consumed in the chip. the sub clock oscillator circuit may also be configured by feeding an externally generated clock to the x cin pin. figure 1.9.8 shows the examples of sub clock connection circuit. after reset, the sub clock is turned off. at this time, the feedback resistor is disconnected from the oscilla- tor circuit. to use the sub clock for the cpu clock, set the cm07 bit of cm0 register to 1 (sub clock) after the sub clock becomes oscillating stably. during stop mode, all clocks including the sub clock are turned off. refer to power control.
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r clock generation circuit 60 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. (3) ring oscillator clock this clock, approximately 1 mhz, is supplied by a ring oscillator. this clock is used as the clock source for the cpu and peripheral function clocks. in addition, if the pm22 bit of pm2 register is 1 (ring oscillator clock for the watchdog timer count source), this clock is used as the count source for the watchdog timer. after reset, the ring oscillator clock is turned off. it is turned on by setting the cm21 bit of cm2 register to 1 (ring oscillator clock), and is used as the clock source for the cpu and peripheral function clocks, in place of the main clock. if the main clock stops oscillating when the cm20 bit of cm2 register is 1 (oscillation stop, re-oscillation detection function enabled) and the cm27 bit is 1 (oscillation stop, re- oscillation detection interrupt), the ring oscillator automatically starts operating, supplying the necessary clock for the microcomputer. (4) pll clock the pll clock is generated from the main clock by a pll frequency synthesizer. this clock is used as the clock source for the cpu and peripheral function clocks. after reset, the pll clock is turned off. the pll frequency synthesizer is activated by setting the plc07 bit to 1 (pll operation). when the pll clock is used as the clock source for the cpu clock, wait t su (pll) for the pll clock to be stable, and then set the cm11 bit in the cm1 register to 1. to enter wait or stop mode, set the cm11 bit to 0 (main clock for the cpu clock source) and then the plc07 bit of plc0 register to 0 (pll off) before entering that mode. figure 1.9.9 shows the procedure for using the pll clock as the clock source for the cpu. the pll clock frequency is determined by the equation below. pll clock frequency=f(x in ) x (multiplying factor set by the plc02 to plc00 bits plc0 register (however, 10 mhz pll clock frequency 24 mhz) the plc02 to plc00 bits can be set only once after reset. table 1.9.2 shows the example for setting pll clock frequencies. x in (mhz) plc02 plc01 plc00 multiplying factor pll clock (mhz)(note) 10001 2 20 5010 4 3.33 0 1 1 6 2.5 1 0 0 8 12 6 4 24 3 001 2 010 4 011 6 100 8 note: 10mhz pll clock frequency 24mhz. table 1.9.2. example for setting pll clock frequencies
clock generation circuit 61 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.9.9. procedure to use pll clock as cpu clock source using the pll clock as the clock source for the cpu set the cm07 bit to 0 (main clock), the cm17 to cm16 bits to 00 2 (main clock undivided), and the cm06 bit to 0 (cm16 and cm17 bits enabled). (note) set the plc02 to plc00 bits (multiplying factor). (to select a 16 mhz or higher pll clock) set the pm20 bit to 0 (2-wait states). set the plc07 bit to 1 (pll operation). wait until the pll clock becomes stable (t su (pll)). set the cm11 bit to 1 (pll clock for the cpu clock source). end note : pll operation mode can be entered from high speed mode.
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r clock generation circuit 62 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. cpu clock and peripheral function clock two type clocks: cpu clock to operate the cpu and peripheral function clocks to operate the peripheral functions. (1) cpu clock and bclk these are operating clocks for the cpu and watchdog timer. the clock source for the cpu clock can be chosen to be the main clock, sub clock, ring oscillator clock or the pll clock. if the main clock or ring oscillator clock is selected as the clock source for the cpu clock, the selected clock source can be divided by 1 (undivided), 2, 4, 8 or 16 to produce the cpu clock. use the cm06 bit in cm0 register and the cm17 to cm16 bits in cm1 register to select the divide-by-n value. when the pll clock is selected as the clock source for the cpu clock, the cm06 bit should be set to 0 and the cm17 to cm16 bits to 00 2 (undivided). after reset, the main clock divided by 8 provides the cpu clock. during memory expansion or microprocessor mode, a bclk signal with the same frequency as the cpu clock can be output from the bclk pin by setting the pm07 bit of pm0 register to 0 (output enabled). note that when entering stop mode from high or middle speed mode, ring oscillator mode or low power ring oscillator mode, or when the cm05 bit of cm0 register is set to 1 (main clock turned off) in low- speed mode, the cm06 bit of cm0 register is set to 1 (divide-by-8 mode). (2) peripheral function clock(f 1 , f 2 , f 8 , f 32 , f 1sio , f 2sio , f 8sio , f 32sio , f ad , f c32 ) these are operating clocks for the peripheral functions. of these, fi (i = 1, 2, 8, 32) and fi sio are derived from the main clock, pll clock or ring oscillator clock by dividing them by i. the clock fi is used for timers a and b, and fi sio is used for serial i/o. the f 8 and f 32 clocks can be output from the clk out pin. the f ad clock is produced from the main clock, pll clock or ring oscillator clock, and is used for the a-d converter. when the wait instruction is executed after setting the cm02 bit of cm0 register to 1 (peripheral function clock turned off during wait mode), or when the microcomputer is in low power dissipation mode, the fi, fi sio and f ad clocks are turned off. the f c32 clock is produced from the sub clock, and is used for timers a and b. this clock can be used when the sub clock is on. clock output function during single-chip mode, the f 8 , f 32 or f c clock can be output from the clk out pin. use the cm01 to cm00 bits of cm0 register to select.
clock generation circuit 63 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. power control there are three power control modes. for convenience sake, all modes other than wait and stop modes are referred to as normal operation mode here. (1) normal operation mode normal operation mode is further classified into seven modes. in normal operation mode, because the cpu clock and the peripheral function clocks both are on, the cpu and the peripheral functions are operating. power control is exercised by controlling the cpu clock frequency. the higher the cpu clock frequency, the greater the processing capability. the lower the cpu clock frequency, the smaller the power consumption in the chip. if the unnecessary oscillator circuits are turned off, the power consumption is further reduced. before the clock sources for the cpu clock can be switched over, the new clock source to which switched must be oscillating stably. if the new clock source is the main clock, sub clock or pll clock, allow a sufficient wait time in a program until it becomes oscillating stably. note that operation modes cannot be changed directly from low speed or low power dissipation mode to ring oscillator or ring oscillator low power dissipation mode. nor can operation modes be changed directly from ring oscillator or ring oscillator low power dissipation mode to low speed or low power dissipation mode. where the cpu clock source is changed from the ring oscillator to the main clock, change the operation mode to the medium speed mode (divided by 8 mode) after the clock was divided by 8 (the cm06 bit of cm0 register was set to 1) in the ring oscillator mode. high-speed mode the main clock divided by 1 provides the cpu clock. if the sub clock is on, f c32 can be used as the count source for timers a and b. pll operation mode the main clock multiplied by 2, 4, 6 or 8 provides the pll clock, and this pll clock serves as the cpu clock. if the sub clock is on, f c32 can be used as the count source for timers a and b. pll operation mode can be entered from high speed mode. if pll operation mode is to be changed to wait or stop mode, first go to high speed mode before changing. medium-speed mode the main clock divided by 2, 4, 8 or 16 provides the cpu clock. if the sub clock is on, f c32 can be used as the count source for timers a and b. low-speed mode the sub clock provides the cpu clock. the main clock is used as the clock source for the peripheral function clock when the cm21 bit is set to 0 (ring oscillator turned off), and the ring oscillator clock is used when the cm21 bit is set to 1 (ring oscillator oscillating). the f c32 clock can be used as the count source for timers a and b. low power dissipation mode in this mode, the main clock is turned off after being placed in low speed mode. the sub clock provides the cpu clock. the f c32 clock can be used as the count source for timers a and b. f c32 is the only peripheral function clock available when the cm21 bit is set to 0 (ring oscillator turned off). if the cm21 bit is set to 1 (ring oscillator oscillating), then f c32 and the ring oscillator clock can be used. simultaneously when this mode is selected, the cm06 bit of cm0 register becomes 1 (divided by 8 mode). in the low power dissipation mode, do not change the cm06 bit. consequently, the medium speed (divided by 8) mode is to be selected when the main clock is operated next.
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r clock generation circuit 64 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. ring oscillator mode the ring oscillator clock divided by 1 (undivided), 2, 4, 8 or 16 provides the cpu clock. the ring oscillator clock is also the clock source for the peripheral function clocks. if the sub clock is on, f c32 can be used as the count source for timers a and b. ring oscillator low power dissipation mode the main clock is turned off after being placed in ring oscillator mode. the cpu clock can be selected as in the ring oscillator mode. the ring oscillator clock is the clock source for the peripheral function clocks. if the sub clock is on, f c32 can be used as the count source for timers a and b. when the operation mode is returned to the high and medium speed modes, set the cm06 bit to 1 (divided by 8 mode). modes cm2 register cm21 cm1 register cm11 cm17, cm16 cm0 register cm07 cm06 cm05 cm04 pll operation mode 0 100 2 00 high-speed mode 0 0 00 2 000 midium- speed mode 0001 2 000 0010 2 000 divided by 2 00 010 0011 2 000 low-speed mode 1 0 1 low power dissipation mode 1 1(note 1) 1 ring oscillator mode 1 divided by 4 divided by 8 divided by 16 ring oscillator low power dissipation mode note 1: when the cm05 bit is set to 1 (main clock turned off) in low-speed mode, the mode goes to low power dissipation mode and cm06 bit is set to 1 (divided by 8 mode) simultaneously. note 2: the divide-by-n value can be selected the same way as in ring oscillator mode. 0 0 101 2 000 110 2 000 1010 111 2 000 100 2 000 (note 2) divided by 2 divided by 4 divided by 8 divided by 16 divided by 1 1(note 1) (note 2) 1 (2) wait mode in wait mode, the cpu clock is turned off, so are the cpu (because operated by the cpu clock) and the watchdog timer. however, if the pm22 bit of pm2 register is 1 (ring oscillator clock for the watchdog timer count source), the watchdog timer remains active. because the main clock, sub clock, ring oscillator clock and pll clock all are on, the peripheral functions using these clocks keep operating. peripheral function clock stop function if the cm02 bit is 1 (peripheral function clocks turned off during wait mode), the f 1 , f 2 , f 8 , f 32 , f 1sio , f 8sio , f 32sio and f ad clocks are turned off when in wait mode, with the power consumption reduced that much. however, f c32 remains on. entering wait mode the microcomputer is placed into wait mode by executing the wait instruction. if the cm11 bit is 1 (pll clock for the cpu clock source), set the cm11 bit to 0 (main clock for the cpu clock source) and then the plc07 bit to 0 (pll turned off) before entering wait mode. pin status during wait mode table 1.9.4 lists pin status during wait mode exiting wait mode ______ the microcomputer is moved out of wait mode by a hardware reset, nmi interrupt or peripheral func- tion interrupt. ______ if the microcomputer is to be moved out of exit wait mode by a hardware reset or nmi interrupt, set the peripheral function interrupt priority ilvl2 to ilvl0 bits to 000 2 (interrupts disabled) before execut- ing the wait instruction. the peripheral function interrupts are affected by the cm02 bit. if cm02 bit is 0 (peripheral function clocks not turned off during wait mode), all peripheral function interrupts can be used to exit wait table 1.9.3. setting clock related bit and modes
clock generation circuit 65 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. table 1.9.4. pin status during wait mode pin memory expansion mode single-chip mode microprocessor mode _______ _______ a 0 to a 19 , d 0 to d 15 , cs0 to cs3, retains status before wait mode ________ bhe _____ ______ ________ _________ rd, wr, wrl, wrh h __________ hlda,bclk h ale h i/o ports retains status before wait mode retains status before wait mode clk out when f c selected does not stop when f 8 , f 32 selected does not stop when the cm02 bit is 0. when the cm02 bit is 1, the status immediately prior to entering wait mode is main- tained. interrupt cm02=0 cm02=1 nmi interrupt can be used serial i/o interrupt can be used when operating with internal or external clock can be used when operating with external clock key input interrupt can be used can be used a-d conversion interrupt can be used in one-shot mode or single sweep mode timer a interrupt can be used in all modes can be used in event counter mode or when the count source is fc32 timer b interrupt int interrupt can be used can be used (do not use) can be used table 1.9.5. interrupts to exit wait mode mode. if cm02 bit is 1 (peripheral function clocks turned off during wait mode), the peripheral func- tions using the peripheral function clocks stop operating, so that only the peripheral functions clocked by external signals can be used to exit wait mode. table 1.9.5 lists the interrupts to exit wait mode. if the microcomputer is to be moved out of wait mode by a peripheral function interrupt, set up the following before executing the wait instruction. 1. in the ilvl2 to ilvl0 bits of interrupt control register, set the interrupt priority level of the periph eral function interrupt to be used to exit wait mode. also, for all of the peripheral function interrupts not used to exit wait mode, set the ilvl2 to ilvl0 bits to 000 2 (interrupt disable). 2. set the i flag to 1. 3. enable the peripheral function whose interrupt is to be used to exit wait mode. in this case, when an interrupt request is generated and the cpu clock is thereby turned on, an interrupt routine is executed. the cpu clock turned on when exiting wait mode by a peripheral function interrupt is the same cpu clock that was on when the wait instruction was executed.
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r clock generation circuit 66 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. (3) stop mode in stop mode, all oscillator circuits are turned off, so are the cpu clock and the peripheral function clocks. therefore, the cpu and the peripheral functions clocked by these clocks stop operating. the least amount of power is consumed in this mode. if the voltage applied to vcc1 and vcc2 pins is v ram or more, the internal ram is retained. when applying 2.7 or less voltage to vcc1 and vcc2 pins, make sure vcc1 vcc2 v ram . however, the peripheral functions clocked by external signals keep operating. the following interrupts can be used to exit stop mode. ______ ? nmi interrupt ? key interrupt ______ ? int interrupt ? timer a, timer b interrupt (when counting external pulses in event counter mode) ? serial i/o interrupt (when external clock is seleted) entering stop mode the microcomputer is placed into stop mode by setting the cm10 bit of cm1 register to 1 (all clocks turned off). at the same time, the cm06 bit of cm0 register is set to 1 (divide-by-8 mode) and the cm15 bit of cm10 register is set to 1 (main clock oscillator circuit drive capability high). before entering stop mode, set the cm20 bit to 0 (oscillation stop, re-oscillation detection function disable). also, if the cm11 bit is 1 (pll clock for the cpu clock source), set the cm11 bit to 0 (main clock for the cpu clock source) and the plc07 bit to 0 (pll turned off) before entering stop mode. pin status in stop mode table 1.9.6 lists pin status during stop mode exiting stop mode ______ the microcomputer is moved out of stop mode by a hardware reset, nmi interrupt or peripheral func- tion interrupt. ______ if the microcomputer is to be moved out of stop mode by a hardware reset or nmi interrupt, set the peripheral function interrupt priority ilvl2 to ilvl0 bits to 000 2 (interrupts disable) before setting the cm10 bit to 1. if the microcomputer is to be moved out of stop mode by a peripheral function interrupt, set up the following before setting the cm10 bit to 1. 1. in the ilvl2 to ilvl0 bits of interrupt control register, set the interrupt priority level of the periph- eral function interrupt to be used to exit stop mode. also, for all of the peripheral function interrupts not used to exit stop mode, set the ilvl2 to ilvl0 bits to 000 2 . 2. set the i flag to 1. 3. enable the peripheral function whose interrupt is to be used to exit stop mode. in this case, when an interrupt request is generated and the cpu clock is thereby turned on, an interrupt service routine is executed. ______ which cpu clock will be used after exiting stop mode by a peripheral function or nmi interrupt is determined by the cpu clock that was on when the microcomputer was placed into stop mode as follows: if the cpu clock before entering stop mode was derived from the sub clock: sub clock if the cpu clock before entering stop mode was derived from the main clock: main clock divide-by-8 if the cpu clock before entering stop mode was derived from the ring oscillator clock: ring oscillator clock divide-by-8
clock generation circuit 67 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. pin memory expansion mode single-chip mode microprocessor mode _______ _______ a 0 to a 19 , d 0 to d 15 , cs0 to cs3, retains status before stop mode ________ bhe _____ ______ ________ _________ rd, wr, wrl, wrh h __________ hlda, bclk h ale h i/o ports retains status before stop mode retains status before stop mode clk out when fc selected h when f 8 , f 32 selected retains status before stop mode table 1.9.6. pin status in stop mode
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r clock generation circuit 68 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.9.10. state transition to stop mode and wait mode reset medium-speed mode (divided-by-8 mode) high-speed, medium- speed mode stop mode wait mode interrupt cm10=1 interrupt normal mode low-speed, low power dissipation mode cm10=1 stop mode interrupt wait mode interrupt cm10=1 stop mode all oscillators stopped interrupt wait mode wait instruction (note 3) interrupt cpu operation stopped when low- speed mode when low power dissipation mode pll operation mode notes 1, 2 note 1: do not go directly from pll operation mode to wait or stop mode. note 2: pll operation mode can be entered from high speed mode. similarly, pll operation mode can be changed back to high speed mode. note 3: when the pm21 bit = 0 (system clock protective function unused). note 4: the ring oscillator clock divided by 8 provides the cpu clock. note 5: write to the cm0 register and cm1 register simultaneously by accessing in word units while cm21=0 (ring oscillator turn ed off). ring oscillator, ring oscillator dissipation mode wait mode interrupt cm10=1 interrupt (note 4) stop mode wait instruction (note 3) wait instruction (note 3) wait instruction (note 3) cm07=0 cm06=1 cm05=0 cm11=0 cm10=1 (note 5) figure 1.9.10 shows the state transition from normal operation mode to stop mode and wait mode. figure 1.9.11 shows the state transition in normal operation mode. table 1.9.7 shows a state transition matrix describing allowed transition and setting. the vertical line shows current state and horizontal line shows state after transition.
clock generation circuit 69 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.9.11. state transition in normal mode cm04=0 cpu clock: f(pll) cm07=0 cm06=0 cm17=0 cm16=0 pll operation mode cm07=0 cm06=0 cm17=0 cm16=0 cm07=0 cm17=0 cm06=0 cm16=0 cm07=0 cm17=0 cm06=0 cm16=1 cm07=0 cm17=1 cm06=0 cm16=0 cm07=0 cm06=1 cm07=0 cm17=1 cm06=0 cm16=1 high-speed mode cm07=0 cm17=0 cm06=0 cm16=0 cm07=0 cm17=0 cm06=0 cm16=1 cm07=0 cm17=1 cm06=0 cm16=0 cm07=0 cm06=1 cm07=0 cm17=1 cm06=0 cm16=1 cm07=0 low-speed mode cm07=0 low power dissipation mode cm06=1 cm15=1 ring oscillator mode cpu clock ring oscillator mode cpu clock cpu clock ring oscillator low power dissipation mode cpu clock cm07=0 low-speed mode cm07=0 low power dissipation mode cm06=1 cm15=1 plc07=1 cm11=1 (note 6) plc07=0 cm11=0 (note 7) cm04=0 plc07=1 cm11=1 plc07=0 cm11=0 cm04=0 cm04=1 cm04=1 cm04=1 cm04=0 cm04=1 cm07=0 (note 2, note 4) cm07=1 (note 3) cm05=1 (note 1) cm05=0 cm05=0 cm05=1 (note 1) cm21=0 (note 8) cm21=1 cm21=0 (note 8) cm21=1 cm21=0 cm21=1 cm21=0 cm21=1 main clock oscillation ring oscillator clock oscillation sub clock oscillation f(ring) f(ring)/2 f(ring)/4 f(ring)/8 f(ring)/16 f(ring) f(ring)/2 f(ring)/4 f(ring)/8 f(ring)/16 f(ring) f(ring)/2 f(ring)/4 f(ring)/8 f(ring)/16 f(ring) f(ring)/2 f(ring)/4 f(ring)/8 f(ring)/16 pll operation mode cpu clock: f(pll) cpu clock: f(x in ) high-speed mode middle-speed mode (divide by 2) cpu clock: f(x in )/2 cpu clock: f(x in )/4 cpu clock: f(x in )/8 cpu clock: f(x in )/16 cpu clock: f(x cin ) cpu clock: f(x cin ) cpu clock: f(x cin ) cpu clock: f(x cin ) cm05=0 m0 m cm05=1 (note 1) cm05=1 (note 1) cm05=0 (note 6) (note 7) middle-speed mode (divide by 4) middle-speed mode (divide by 8) middle-speed mode (divide by 16) middle-speed mode (divide by 2) middle-speed mode (divide by 4) middle-speed mode (divide by 8) middle-speed mode (divide by 16) cpu clock: f(x in ) cpu clock: f(x in )/2 cpu clock: f(x in )/4 cpu clock: f(x in )/8 cpu clock: f(x in )/16 ring oscillator low power dissipation mode notes: 1: avoid making a transition when the cm20 bit is set to 1 (oscillation stop, re-oscillation detection function enabled). set the cm20 bit to 0 (oscillation stop, re-oscillation detection function disabled) before transiting. 2: switch clock after oscillation of main clock is sufficiently stable. 3: switch clock after oscillation of sub-clock is sufficiently stable. 4: change cm17 and cm16 before changing cm06. 5: transit in accordance with arrow. 6: pll operation mode can only be entered from high speed mode. also, wait until the pll clock is sufficiently stable before changing operation modes. to select a 16 mhz or higher pll clock, set the pm20 bit to 0 (sfr accessed with two wait states) before setting plc07 t o 1 (pll operation). 7: pll operation mode can only be changed to high speed mode. if the pm20 bit = 0 (sfr accessed with two wait states), set plc 07 to 0 (pll turned off) before setting the pm20 bit to 1 (sfr accessed with one wait state). 8: set the cm06 bit to 1 (division by 8 mode) before changing back the operation mode from ring oscillator mode to high- or middle-speed mode.
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r clock generation circuit 70 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. table 1.9.7. allowed transition and setting high-speed mode, middle-speed mode ring oscillator mode stop mode wait mode ring oscillator low power dissipation mode pll operation mode 2 low power dissipation mode 2 low-speed mode 2 current state state after transition see table a -- (8) (18) 5 (3) (3) (3) (3) (4) (4) (4) (4) (5) (7) (7) (5) (5) (5) (7) (7) (6) (6) (6) (6) no division divided by 2 (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) setting operation cm04 = 0 sub clock turned off cm04 = 1 sub clock oscillating cm06 = 0, cpu clock no division mode cm17 = 0 , cm16 = 0 cm06 = 0, cpu clock division by 2 mode cm17 = 0 , cm16 = 1 cm06 = 0, cpu clock division by 4 mode cm17 = 1 , cm16 = 0 cm06 = 1 cpu clock division by 8 mode cm06 = 0, cpu clock division by 16 mode cm17 = 1 , cm16 = 1 cm07 = 0 main clock, pll clock, or ring oscillator clock selected cm07 = 1 sub clock selected cm05 = 0 main clock oscillating cm05 = 1 main clock turned off plc07 = 0, cm11 = 0 main clock selected plc07 = 1, cm11 = 1 pll clock selected cm21 = 0 main clock or pll clock selected cm21 = 1 ring oscillator clock selected cm10 = 1 transition to stop mode wait transition to wait mode hardware interrupt exit stop mode or wait mode (9) 7 -- (10) (11) 1, 6 (12) 3 (14) 4 -- -- -- -- -- (13) 3 (15) -- -- -- -- -- -- -- (10) -- -- -- -- -- -- -- -- (18) (18) -- -- (16) 1 (17) (16) 1 (17) (16) 1 (17) (16) 1 (17) (16) 1 (17) -- -- (3) (3) (3) (3) (4) (4) (4) (4) (5) (5) (5) (5) (7) (7) (7) (7) (6) (6) (6) (6) (1) (1) (1) (1) (1) (2) (2) (2) (2) (2) -- -- -- -- -- -- ---- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- sub clock oscillating sub clock turned off (18) 5 (18) 5 (18) (18)(18) (18)(18) table 1. state transition with main clock division ration in high- or middle-speed mode, ring oscillator mode, and ring oscillator low power dissipation mode table b. setting and operation notes: 1. avoid making a transition when the cm21 bit is set to 1 (oscillation stop, re-oscillation detection function enabled). set the cm21 bit to 0 (oscillation stop, re-oscillation detection function disabled) before transiting. 2. ring oscillator clock oscillates and stops in low-speed mode and low power dissipation mode. in these mode, the ring oscillator can be used as peripheral function clock. sub clock oscillates and stops in pll operation mode. in this mode, sub clock can be used as peripheral function clock. 3. pll operation mode can only be entered from and changed to high-speed mode. 4. set the cm06 bit to 1 (division by 8 mode) before transiting from ring oscillator mode to high- or middle-speed mode. 5. when exiting stop mode, the cm06 bit is set to 1 (division by 8 mode). 6. if the cm05 bit is set to 1 (main clock stop), then the cm06 bit is set to 1 (division by 8 mode). 7. a transition can be made only when sub clock is oscillating. --: cannot transit (11) 1 --: cannot transit high-speed mode, middle-speed mode ring oscillator mode stop mode wait mode ring oscillator low power dissipation mode pll operation mode 1 low power dissipation mode 1 low-speed mode 1 see table a see table a divided by 4 divided by 8 divided by 16 no division divided by 2 divided by 4 divided by 8 divided by 16 no division divided by 4 sub clock oscillating sub clock turned off divided by 8 divided by 16 divided by 2 no division divided by 4 divided by 8 divided by 16 divided by 2
clock generation circuit 71 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. system clock protective function when the main clock is selected for the cpu clock source, this function disables the clock against modifica- tions in order to prevent the cpu clock from becoming halted by run-away. if the pm21 bit of pm2 register is set to 1 (clock modification disabled), the following bits are protected against writes: ? cm02, cm05, and cm07 bits in cm0 register ? cm10, cm11 bits in cm1 register ? cm20 bit in cm2 register ? all bits in plc0 register before the system clock protective function can be used, the following register settings must be made while the cm05 bit of cm0 register is 0 (main clock oscillating) and cm07 bit is 0 (main clock selected for the cpu clock source): (1) set the prc1 bit of prcr register to 1 (enable writes to pm2 register). (2) set the pm21 bit of pm2 register to 1 (disable clock modification). (3) set the prc1 bit of prcr register to 0 (disable writes to pm2 register). do not execute the wait instruction when the pm21 bit is 1.
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r clock generation circuit 72 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. oscillation stop and re-oscillation detect function the oscillation stop and re-oscillation detect function is such that main clock oscillation circuit stop and re- oscillation are detected. at oscillation stop, re-oscillation detection, reset or oscillation stop, re-oscillation detection interrupt are generated. which is to be generated can be selected using the cm27 bit of cm2 register. table 1.9.4 lists an specification overview of the oscillation stop and re-oscillation detect function. table 1.9.7. specification overview of oscillation stop and re-oscillation detect function item specification oscillation stop detectable clock and f(x in ) 2 mhz frequency bandwidth enabling condition for oscillation stop, set cm20 bit to 1(enable) re-oscillation detection function operation at oscillation stop, ?reset occurs (when cm27 bit =0) re-oscillation detection ? oscillation stop, re-oscillation detection interrupt occurs(when cm27 bit =1) (1) operation when cm27 bit = 0 (oscillation stop detection reset) where main clock stop is detected when the cm20 bit is 1 (oscillation stop, re-oscillation detection function enabled), the microcomputer is initialized, coming to a halt (oscillation stop reset; refer to sfr, reset). this status is reset with hardware reset 1 or hardware reset 2. also, even when re-oscillation is detected, the microcomputer can be initialized and stopped; it is, however, necessary to avoid such usage. (during main clock stop, do not set the cm20 bit to 1 and the cm27 bit to 0.) (2) operation when cm27 bit = 0 (oscillation stop and re-oscillation detect interrupt) where the main clock corresponds to the cpu clock source and the cm20 bit is 1 (oscillation stop and re-oscillation detect function enabled), the system is placed in the following state if the main clock comes to a halt: ? oscillation stop and re-oscillation detect interrupt request occurs. ? the ring oscillator starts oscillation, and the ring oscillator clock becomes the cpu clock and clock source for peripheral functions in place of the main clock. ? cm21 bit = 1 (ring oscillator clock for cpu clock source) ? cm22 bit = 1 (main clock stop detected) ? cm23 bit = 1 (main clock stopped) where the pll clock corresponds to the cpu clock source and the cm20 bit is 1, the system is placed in the following state if the main clock comes to a halt: since the cm21 bit remains unchanged, set it to 1 (ring oscillator clock) inside the interrupt routine. ? oscillation stop and re-oscillation detect interrupt request occurs. ? cm22 bit = 1 (main clock stop detected) ? cm23 bit = 1 (main clock stopped) ? cm21 bit remains unchanged where the cm20 bit is 1, the system is placed in the following state if the main clock re-oscillates from the stop condition: ? oscillation stop and re-oscillation detect interrupt request occurs. ? cm22 bit = 1 (main clock re-oscillation detected) ? cm23 bit = 0 (main clock oscillation) ? cm21 bit remains unchanged
clock generation circuit 73 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. how to use oscillation stop and re-oscillation detect function ? the oscillation stop and re-oscillation detect interrupt shares the vector with the watchdog timer inter- rupt. if the re-oscillation detection and watchdog timer interrupts both are used, read the cm22 bit in an interrupt routine to determine which interrupt source is requesting the interrupt. ? where the main clock re-oscillated after oscillation stop, return the main clock to the cpu clock and peripheral function clock source in the program. figure 1.9.12 shows the procedure for switching the clock source from the ring oscillator to the main clock. ? simultaneously with oscillation stop, re-oscillation detection interrupt occurrence, the cm22 bit be- comes 1. when the cm22 bit is set at 1, oscillation stop, re-oscillation detection interrupt are dis- abled. by setting the cm22 bit to 0 in the program, oscillation stop, re-oscillation detection interrupt are enabled. ? if the main clock stops during low speed mode where the cm20 bit is 1, an oscillation stop, re-oscilla- tion detection interrupt request is generated. at the same time, the ring oscillator starts oscillating. in this case, although the cpu clock is derived from the sub clock as it was before the interrupt occurred, the peripheral function clocks now are derived from the ring oscillator clock. ? to enter wait mode while using the oscillation stop, re-oscillation detection function, set the cm02 bit to 0 (peripheral function clocks not turned off during wait mode). ? since the oscillation stop , re-oscillation detection function is provided in preparation for main clock stop due to external factors, set the cm20 bit to 0 (oscillation stop , re-oscillation detection function dis- abled) where the main clock is stopped or oscillated in the program, that is where the stop mode is selected or the cm05 bit is altered. ? this function cannot be used if the main clock frequency is 2 mhz or less. in that case, set the cm20 bit to 0. figure 1.9.12. procedure to switch clock source from ring oscillator to main clock main clock switch inspect the cm23 bit do this check a number of times set the cm22 bit to 0 (main clock stop, re-oscillation not detected). set the cm21 bit to 0 (main clock for the cpu clock source)(note) 1(main clock stop) 0(main clock oscillation) the main clock is confirmed to be active a number of times. all of cm21-23 are the cm2 register bits end note: if the clock source for cpu clock is to be changed to pll clock, set to pll operation mode after set to high-speed mode.
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r 74 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. protection protection in the event that a program runs out of control, this function protects the important registers so that they will not be rewritten easily. figure 1.10.1 shows the prcr register. the following lists the registers protected by the prcr register. ? registers protected by prc0 bit: cm0, cm1, cm2, plc0 and pclkr registers ? registers protected by prc1 bit: pm0, pm1, pm2, tb2sc, invc0 and invc1 registers ? registers protected by prc2 bit: pd9, s3c and s4c registers ? registers protected by prc3 bit: vcr2 and d4int registers set the prc2 bit to 1 (write enabled) and then write to any address, and the prc2 bit will be cleared to 0 (write protected). the registers protected by the prc2 bit should be changed in the next instruction after setting the prc2 bit to 1. make sure no interrupts or dma transfers will occur between the instruction in which the prc2 bit is set to 1 and the next instruction. the prc0, prc1 and prc3 bits are not automati- cally cleared to 0 by writing to any address. they can only be cleared in a program. protect register symbol address after reset prcr 000a 16 xx000000 2 bit namebit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 : write protected 1 : write enabled prc1 prc0 prc2 function rw note: the prc2 bit is set to 0 by writing to any address after setting it to 1. other bits are not set to 0 by writing to any address, and must therefore be set in a program. 0 rw rw rw nothing is assigned. when write, set to 0. when read, its content is interdeterminate. reserved bit must set to 0 rw protect bit 0 protect bit 1 protect bit 2 enable write to cm0, cm1, cm2, plc0 and pclkr registers 0 : write protected 1 : write enabled enable write to pm0, pm1, pm2, tb2sc, invc0 and invc1 registers 0 : write protected 1 : write enabled enable write to pd9, s3c and s4c registers prc3 rw protect bit 3 0 : write protected 1 : write enabled enable write to vcr2 and d4int registers (b5-b4) (b7-b6) 0 figure 1.10.1. prcr register
interrupts 75 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. ? maskable interrupt: an interrupt which can be enabled (disabled) by the interrupt enable flag (i flag) or whose interrupt priority can be changed by priority level. ? non-maskable i0nterrupt: an interrupt which cannot be enabled (disabled) by the interrupt enable flag (i flag) or whose interrupt priority cannot be changed by priority level. figure 1.11.1. interrupts interrupt ? ? ? ? ? ? ? ? ? software (non-maskable interrupt) hardware ? ? ? ? ? special (non-maskable interrupt) peripheral function (note 1) (maskable interrupt) ? ? ? ? ? undefined instruction (und instruction) overflow (into instruction) brk instruction int instruction ? ? ? ? ? ? ? _______ nmi ________ dbc (note 2) watchdog timer single step (note 2) address match note 1: peripheral function interrupts are generated by the microcomputer's internal functions. note 2: do not normally use this interrupt because it is provided exclusively for use by development support tools. interrupts type of interrupts figure 1.11.1 shows types of interrupts.
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r interrupts 76 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. software interrupts a software interrupt occurs when executing certain instructions. software interrupts are non-maskable interrupts. undefined instruction interrupt an undefined instruction interrupt occurs when executing the und instruction. overflow interrupt an overflow interrupt occurs when executing the into instruction with the o flag set to 1 (the opera- tion resulted in an overflow). the following are instructions whose o flag changes by arithmetic: abs, adc, adcf, add, cmp, div, divu, divx, neg, rmpa, sbb, sha, sub brk interrupt a brk interrupt occurs when executing the brk instruction. int instruction interrupt an int instruction interrupt occurs when executing the int instruction. software interrupt nos. 0 to 63 can be specified for the int instruction. because software interrupt nos. 4 to 31 are assigned to peripheral function interrupts, the same interrupt routine as for peripheral function interrupts can be executed by executing the int instruction. in software interrupt nos. 0 to 31, the u flag is saved to the stack during instruction execution and is cleared to 0 (isp selected) before executing an interrupt sequence. the u flag is restored from the stack when returning from the interrupt routine. in software interrupt nos. 32 to 63, the u flag does not change state during instruction execution, and the sp then selected is used.
interrupts 77 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. hardware interrupts hardware interrupts are classified into two types special interrupts and peripheral function interrupts. (1) special interrupts special interrupts are non-maskable interrupts. _______ nmi interrupt _______ _______ an nmi interrupt is generated when input on the nmi pin changes state from high to low. for details _______ about the nmi interrupt, refer to the section "nmi interrupt". ________ dbc interrupt do not normally use this interrupt because it is provided exclusively for use by development support tools. watchdog timer interrupt generated by the watchdog timer. once a watchdog timer interrupt is generated, be sure to initialize the watchdog timer. for details about the watchdog timer, refer to the section "watchdog timer". oscillation stop and re-oscillation detection interrupt generated by the oscillation stop and re-oscillation detection function. for details about the oscilla- tion stop detection function, refer to the section "clock generating circuit". power supply down detection interrupt generated by the voltage detection circuit. for details about the voltage detection circuit, refer to the section "voltage detection circuit". single-step interrupt do not normally use this interrupt because it is provided exclusively for use by development support tools. address match interrupt an address match interrupt is generated immediately before executing the instruction at the address indicated by the rmad0 to rmad3 register that corresponds to one of the aier registers aier0 or aier1 bit or the aier2 registers aier20 or aier21 bit which is "1" (address match interrupt en- abled). for details about the address match interrupt, refer to the section "address match interrupt". (2) peripheral function interrupts peripheral function interrupts are maskable interrupts and generated by the microcomputer's internal functions. the interrupt sources for peripheral function interrupts are listed in table 1.11.2. for details about the peripheral functions, refer to the description of each peripheral function in this manual.
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r interrupts 78 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. interrupt source vector table addresses remarks reference address (l) to address (h) undefined instruction fffdc 16 to fffdf 16 interrupt on und instruction m16c/60, m16c/20 overflow fffe0 16 to fffe3 16 interrupt on into instruction serise software brk instruction fffe4 16 to fffe7 16 maual address match fffe8 16 to fffeb 16 address match interrupt single step (note) fffec 16 to fffef 16 watchdog timer ffff0 16 to ffff3 16 watchdog timer oscillation stop and re-oscillation detection clock generating circuit power supply down detection voltage detection circuit ________ dbc (note) ffff4 16 to ffff7 16 _______ nmi ffff8 16 to ffffb 16 _______ nmi interrupt reset ffffc 16 to fffff 16 reset note: do not normally use this interrupt because it is provided exclusively for use by development sup- port tools. figure 1.11.2. interrupt vector aaaaaaaaa aaaaaaaaa mid address aaaaaaaaa aaaaaaaaa low address aaaaaaaaa aaaaaaaaa 0 0 0 0 high address aaaaaaaaa aaaaaaaaa 0 0 0 0 0 0 0 0 vector address (l) lsb msb vector address (h) interrupts and interrupt vector one interrupt vector consists of 4 bytes. set the start address of each interrupt routine in the respective interrupt vectors. when an interrupt request is accepted, the cpu branches to the address set in the corresponding interrupt vector. figure 1.11.2 shows the interrupt vector. fixed vector tables the fixed vector tables are allocated to the addresses from fffdc 16 to fffff 16 . table 1.11.1 lists the fixed vector tables. in the flash memory version of microcomputer, the vector addresses (h) of fixed vectors are used by the id code check function. for details, refer to the section "flash memory rewrite disabling function". table 1.11.1. fixed vector tables if the contents of address fffe7 16 is ff 16 , program ex- ecution starts from the address shown by the vector in the relocatable vector table.
interrupts 79 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. table 1.11.2. relocatable vector tables software interrupt number reference note 1: address relative to address in intb. note 2: use the ifsr register's ifsr6 and ifsr7 bits to select. note 3: during i 2 c mode, nack and ack interrupts comprise the interrupt source. note 4: use the ifsr2a registers ifsr26 and ifsr27 bits to select. note 5: these interrupts cannot be disabled using the i flag. vector address (note 1) address (l) to address (h) 0 11 12 13 14 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 63 to 10 15 16 5 6 7 8 4 9 1 to 3 interrupt source brk instruction int3 si/o3, int4 si/o4, int5 timer b4, uart1 bus collision detect timer b5 (note 2) (note 2) dma0 dma1 key input interrupt a-d uart0 transmit, nack0 uart0 receive, ack0 uart1 transmit, nack1 uart1 receive, ack1 timer a0 timer a1 timer a2 timer a3 timer a4 timer b0 timer b1 timer b2 int0 int1 int2 software interrupt uart 2 bus collision detection uart2 transmit, nack2 (note 3) uart2 receive, ack2 (note 3) ( note 4 ) timer b3, uart0 bus collision detect ( note 4 ) m16c/60, m16c/20 series software manual int interrupt timer timer serial i/o serial i/o int interrupt serial i/o dmac key input interrupt a-d convertor serial i/o timer int interrupt m16c/60, m16c/20 series software manual (note 5) (reserved) +0 to +3 (0000 16 to 0003 16 ) +44 to +47 (002c 16 to 002f 16 ) +48 to +51 (0030 16 to 0033 16 ) +52 to +55 (0034 16 to 0037 16 ) +56 to +59 (0038 16 to 003b 16 ) +68 to +71 (0044 16 to 0047 16 ) +72 to +75 (0048 16 to 004b 16 ) +76 to +79 (004c 16 to 004f 16 ) +80 to +83 (0050 16 to 0053 16 ) +84 to +87 (0054 16 to 0057 16 ) +88 to +91 (0058 16 to 005b 16 ) +92 to +95 (005c 16 to 005f 16 ) +96 to +99 (0060 16 to 0063 16 ) +100 to +103 (0064 16 to 0067 16 ) +104 to +107 (0068 16 to 006b 16 ) +108 to +111 (006c 16 to 006f 16 ) +112 to +115 (0070 16 to 0073 16 ) +116 to +119 (0074 16 to 0077 16 ) +120 to +123 (0078 16 to 007b 16 ) +124 to +127 (007c 16 to 007f 16 ) +128 to +131 (0080 16 to 0083 16 ) +252 to +255 (00fc 16 to 00ff 16 ) +40 to +43 (0028 16 to 002b 16 ) +60 to +63 (003c 16 to 003f 16 ) +64 to +67 (0040 16 to 0043 16 ) +20 to +23 (0014 16 to 0017 16 ) +24 to +27 (0018 16 to 001b 16 ) +28 to +31 (001c 16 to 001f 16 ) +32 to +35 (0020 16 to 0023 16 ) +16 to +19 (0010 16 to 0013 16 ) +36 to +39 (0024 16 to 0027 16 ) to (note 3) (note 3) (note 3) (note 3) (note 5) relocatable vector tables the 256 bytes beginning with the start address set in the intb register comprise a reloacatable vector table area. table 1.11.2 lists the relocatable vector tables. setting an even address in the intb regis- ter results in the interrupt sequence being executed faster than in the case of odd addresses.
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r interrupts 80 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. interrupt control the following describes how to enable/disable the maskable interrupts, and how to set the priority in which order they are accepted. what is explained here does not apply to nonmaskable interrupts. use the flg registers i flag, ipl, and each interrupt control registers ilvl2 to ilvl0 bits to enable/disable the maskable interrupts. whether an interrupt is requested is indicated by the ir bit in each interrupt control register. figure 1.11.3 shows the interrupt control registers.
interrupts 81 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.11.3. interrupt control registers symbol address a fter reset int3ic (note 4) 0044 16 xx00x000 2 s4ic/int5ic 0048 16 xx00x000 2 s3ic/int4ic 0049 16 xx00x000 2 int0ic to int2ic 005d 16 to 005f 16 xx00x000 2 bit name functionbit symbol b7 b6 b5 b4 b3 b2 b1 b0 a aa ilvl0 ir pol no functions are assigned. when writing to these bits, write 0. the values in these bits when read are indeterminate. interrupt priority level select bit interrupt request bit polarity select bit reserved bit 0: interrupt not requested 1: interrupt requested 0 : selects falling edge (notes 3, 5) 1 : selects rising edge must always be set to 0 ilvl1 ilvl2 note 1: this bit can only be reset by writing "0" (do not write "1"). note 2: to rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. for details, see the precautions for interrupts. note 3: if the ifsr register?s ifsri bit (i = 0 to 5) is "1" (both edges), set the intiic register?s pol bit to "0 "(falling edge). note 4: during memory expansion and microprocessor modes, set the int3ic register?s ilvl2 to ilvl0 bits to ?000 2 ? (interrupt disabled). note 5: set the s3ic or s4ic register?s pol bit to "0" (falling edge) when the ifsr register?s ifsr6 bit = 0 (si/o3 selected) or ifsr7 bit = 0 (si/o4 selected), respectively. (note 1) interrupt control register (note 2) b7 b6 b5 b4 b3 b2 b1 b0 a a aa aa a a aa aa bit name function bit symbol rw symbol address after reset tb5ic 0045 16 xxxxx000 2 tb4ic/u1bcnic (note 3) 0046 16 xxxxx000 2 tb3ic/u0bcnic (note 3) 0047 16 xxxxx000 2 bcnic 004a 16 xxxxx000 2 dm0ic, dm1ic 004b 16 , 004c 16 xxxxx000 2 kupic 004d 16 xxxxx000 2 adic 004e 16 xxxxx000 2 s0tic to s2tic 0051 16 , 0053 16 , 004f 16 xxxxx000 2 s0ric to s2ric 0052 16 , 0054 16 , 0050 16 xxxxx000 2 ta0ic to ta4ic 0055 16 to 0059 16 xxxxx000 2 tb0ic to tb2ic 005a 16 to 005c 16 xxxxx000 2 ilvl0 ir interrupt priority level select bit interrupt request bit 0 : interrupt not requested 1 : interrupt requested ilvl1 ilvl2 no functions are assigned. when writing to these bits, write 0. the values in these bits when read are indeterminate. (note 1) note 1: this bit can only be reset by writing "0" (do not write "1"). note 2: to rewrite the interrupt control registers, do so at a point that does not generate the interrupt request for that register. for details, see the precautions for interrupts. note 3: use the ifsr2a register to select. 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b2 b1 b0 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b2 b1 b0 0 rw rw rw rw (b7-b4) rw rw rw rw rw rw rw rw (b7-b6)
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r interrupts 82 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. i flag the i flag enables or disables the maskable interrupt. setting the i flag to 1 (= enabled) enables the maskable interrupt. setting the i flag to 0 (= disabled) disables all maskable interrupts. ir bit the ir bit is set to 1 (= interrupt requested) when an interrupt request is generated. then, when the interrupt request is accepted and the cpu branches to the corresponding interrupt vector, the ir bit is cleared to 0 (= interrupt not requested). the ir bit can be cleared to 0 in a program. note that do not write 1 to this bit. table 1.11.4. interrupt priority levels enabled by ipl table 1.11.3. settings of interrupt priority levels ilvl2 to ilvl0 bits interrupt priority level priority order 000 2 001 2 010 2 011 2 100 2 101 2 110 2 111 2 level 0 (interrupt disabled) level 1 level 2 level 3 level 4 level 5 level 6 level 7 low high enabled interrupt priority levels interrupt levels 1 and above are enabled interrupt levels 2 and above are enabled interrupt levels 3 and above are enabled interrupt levels 4 and above are enabled interrupt levels 5 and above are enabled interrupt levels 6 and above are enabled interrupt levels 7 and above are enabled all maskable interrupts are disabled ipl 000 2 001 2 010 2 011 2 100 2 101 2 110 2 111 2 ilvl2 to ilvl0 bits and ipl interrupt priority levels can be set using the ilvl2 to ilvl0 bits. table 1.11.3 shows the settings of interrupt priority levels and table 1.11.4 shows the interrupt priority levels enabled by the ipl. the following are conditions under which an interrupt is accepted: i flag = 1 ir bit = 1 interrupt priority level > ipl the i flag, ir bit, ilvl2 to ilvl0 bits and ipl are independent of each other. in no case do they affect one another.
interrupts 83 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. interrupt sequence an interrupt sequence what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed is described here. if an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. if an interrupt occurs during execution of either the smovb, smovf, sstr or rmpa instruction, the processor temporarily suspends the instruction being executed, and transfers control to the interrupt sequence. the cpu behavior during the interrupt sequence is described below. figure 1.11.4 shows time required for executing the interrupt sequence. (1) the cpu gets interrupt information (interrupt number and interrupt request priority level) by reading the address 00000 16 . then it clears the ir bit for the corresponding interrupt to 0 (interrupt not re- quested). (2) the flg register immediately before entering the interrupt sequence is saved to the cpus internal temporary register (note 1) . (3) the i, d and u flags in the flg register become as follows: the i flag is cleared to 0 (interrupts disabled). the d flag is cleared to 0 (single-step interrupt disabled). the u flag is cleared to 0 (isp selected). however, the u flag does not change state if an int instruction for software interrupt nos. 32 to 63 is executed. (4) the cpus internal temporary register (note 1) is saved to the stack. (5) the pc is saved to the stack. (6) the interrupt priority level of the accepted interrupt is set in the ipl. (7) the start address of the relevant interrupt routine set in the interrupt vector is stored in the pc. after the interrupt sequence is completed, the processor resumes executing instructions from the start address of the interrupt routine. note: this register cannot be used by user. indeterminate 123456789 1011 12 13 14 15 16 17 18 indeterminate sp-2 contents sp-4 contents vec contents vec+2 contents interrupt information address 0000 16 indeterminate s p-2 s p-4 v ec vec+2 pc cpu clock address bus data bus wr rd the indeterminate state depends on the instruction queue buffer. a read cycle occurs when the instruction queue buffer is ready to accept instructions. figure 1.11.4. time required for executing interrupt sequence
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r interrupts 84 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. interrupt sources 7 level that is set to ipl _______ watchdog timer, nmi _________ software, address match, dbc, single-step not changed variation of ipl when interrupt request is accepted when a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the ipl. when a software interrupt or special interrupt request is accepted, one of the interrupt priority levels listed in table 1.11.5 is set in the ipl. shown in table 1.11.5 are the ipl values of software and special interrupts when they are accepted. table 1.11.5. ipl level that is set to ipl when a software or special interrupt is accepted instruction interrupt sequence instruction in interrupt routine time interrupt response time (a) (b) interrupt request acknowledged interrupt request generated (a) a time from when an interrupt request is generated till when the instruction then executing is completed. the length of this time varies with the instruction being executed. the divx instruction requires the longest time, which is equal to 30 cycles (without wait state, the divisor being a register). (b) a time during which the interrupt sequence is executed. for details, see the table below. note, however, that the values in this table must be increased 2 cycles for the dbc interrupt and 1 cycle for the address match and single-step interrupts. interrupt vector address even even odd odd sp value even odd even odd 16-bit bus, without wait 18 cycles 19 cycles 19 cycles 20 cycles 8-bit bus, without wait 20 cycles 20 cycles 20 cycles 20 cycles figure 1.11.5. interrupt response time interrupt response time figure 1.11.5 shows the interrupt response time. the interrupt response or interrupt acknowledge time denotes a time from when an interrupt request is generated till when the first instruction in the interrupt routine is executed. specifically, it consists of a time from when an interrupt request is generated till when the instruction then executing is completed ((a) in figure 1.11.5) and a time during which the interrupt sequence is executed ((b) in figure 1.11.5).
interrupts 85 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. saving registers in the interrupt sequence, the flg register and pc are saved to the stack. at this time, the 4 high-order bits of the pc and the 4 high-order (ipl) and 8 low-order bits of the flg register, 16 bits in total, are saved to the stack first. next, the 16 low-order bits of the pc are saved. figure 1.11.6 shows the stack status before and after an interrupt request is accepted. the other necessary registers must be saved in a program at the beginning of the interrupt routine. use the pushm instruction, and all registers except sp can be saved with a single instruction. address content of previous stack stack [sp] spvalue before interrupt occurs m m C 1 m C 2 m C 3 m C 4 stack status before interrupt request is acknowledged stack status after interrupt request is acknowledged content of previous stack m + 1 msb lsb m m C 1 m C 2 m C 3 m C 4 address flg l content of previous stack stack flg h pc h [sp] new sp value content of previous stack m + 1 msb lsb pc l pc m figure 1.11.6. stack statusbefore and after acceptance of interrupt request
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r interrupts 86 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.11.7. operation of saving register (2) sp contains odd number [sp] (odd) [sp] C 1 (even) [sp] C 2(odd) [sp] C 3 (even) [sp] C 4(odd) [sp] C 5 (even) address sequence in which order registers are saved (2) (1) finished saving registers in four operations. (3) (4) (1) sp contains even number [sp] (even) [sp] C 1(odd) [sp] C 2 (even) [sp] C 3(odd) [sp] C 4 (even) [sp] C 5 (odd) note: [sp] denotes the initial value of the sp when interrupt request is acknowledged. after registers are saved, the sp content is [sp] minus 4. address pc m stack flg l pc l sequence in which order registers are saved (2) saved simultaneously, all 16 bits (1) saved simultaneously, all 16 bits finished saving registers in two operations. pc m stack flg l pc l saved, 8 bits at a time flg h pc h flg h pc h the operation of saving registers carried out in the interrupt sequence is dependent on whether the sp (note) , at the time of acceptance of an interrupt request, is even or odd. if the stack pointer (note) is even, the flg register and the pc are saved, 16 bits at a time. if odd, they are saved in two steps, 8 bits at a time. figure 1.11.7 shows the operation of the saving registers. note: when any int instruction in software numbers 32 to 63 has been executed, this is the sp indicated by the u flag. otherwise, it is the isp.
interrupts 87 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. interrupt priority if two or more interrupt requests are generated while executing one instruction, the interrupt request that has the highest priority is accepted. for maskable interrupts (peripheral functions), any desired priority level can be selected using the ilvl2 to ilvl0 bits. however, if two or more maskable interrupts have the same priority level, their interrupt priority is resolved by hardware, with the highest priority interrupt accepted. the watchdog timer and other special interrupts have their priority levels set in hardware. figure 1.11.8 shows the priorities of hardware interrupts. software interrupts are not affected by the interrupt priority. if an instruction is executed, control branches invariably to the interrupt routine. returning from an interrupt routine the flg register and pc in the state in which they were immediately before entering the interrupt se- quence are restored from the stack by executing the reit instruction at the end of the interrupt routine. thereafter the cpu returns to the program which was being executed before accepting the interrupt re- quest. return the other registers saved by a program within the interrupt routine using the popm or similar in- struction before executing the reit instruction. interrupt priority resolution circuit the interrupt priority resolution circuit is used to select the interrupt with the highest priority among those requested. figure 1.11.9 shows the circuit that judges the interrupt priority level. figure 1.11.8. hardware interrupt priority _______ ________ reset > nmi > dbc > wdt > peripheral function > single step > address match
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r interrupts 88 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.11.9. interrupts priority select circuit timer b2 timer b0 timer a3 timer a1 timer b1 timer a4 timer a2 uart1 reception, ack1 uart0 reception, ack0 uart2 reception, ack2 a-d conversion dma1 uart 2 bus collision timer a0 uart1 transmission, nack1 uart0 transmissionm, nack0 uart2 transmission, nack2 key input interrupt dma0 ipl i flag int1 int2 int0 watchdog timer dbc nmi interrupt request accepted level 0 (initial value) priority level of each interrupt high low priority of peripheral fucntion interrupts (if priority levels are same) timer b4, uart1 bus collision int3 timer b3, uart0 bus collision timer b5 si/o4, int5 si/o3, int4 address match interrupt request level resolution output to clock generating circuit (fig.1.11.1) oscillation stop and re-oscillation detection power supply down detection
interrupts 89 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. ______ int interrupt _______ inti interrupt (i=0 to 5) is triggered by the edges of external inputs. the edge polarity is selected using the ifsr register's ifsri bit. _______ _______ int4 and int5 share the interrupt vector and interrupt control register with si/o3 and si/o4, respectively. _______ _______ _______ to use the int4 interrupt, set the ifsr registers ifsr6 bit to 1 (= int4). to use the int5 interrupt, set the _______ ifsr registers ifsr7 bit to 1 (= int5). after modifying the ifsr6 or ifsr7 bit, clear the corresponding ir bit to 0 (= interrupt not requested) before enabling the interrupt. figure 1.11.10 shows the ifsr and ifsr2a registers. figure 1.11.10. ifsr register and ifsr2a register interrupt request cause select register bit name function bit symbol rw symbol address a fter reset ifsr 035f 16 00 16 ifsr0 b7 b6 b5 b4 b3 b2 b1 b0 aa aa a a aa aa aa aa int0 interrupt polarity switching bit 0 : si/o3 1 : int4 0 : si/o4 1 : int5 0 : one edge 1 : both edges 0 : one edge 1 : both edges 0 : one edge 1 : both edges 0 : one edge 1 : both edges 0 : one edge 1 : both edges int1 interrupt polarity switching bit int2 interrupt polarity switching bit int3 interrupt polarity switching bit int4 interrupt polarity switching bit int5 interrupt polarity switching bit 0 : one edge 1 : both edges interrupt request cause select bit interrupt request cause select bit ifsr1 ifsr2 ifsr3 ifsr4 ifsr5 ifsr6 ifsr7 rw rw rw rw rw rw rw rw (note 1) (note 1) (note 1) (note 1) (note 1) (note 1) (note 3) (note 2) (note 2) note 1: when setting this bit to 1 (= both edges), make sure the int0ic to int5ic register?s pol bit is set to 0 (= falling edge). note 2: during memory expansion and microprocessor modes, set this bit to 0 (= si/o3, si/o4) note 3: when setting this bit to 0 (= si/o3, si/o4), make sure the s3ic and s4ic registers? pol bit is set to 0 (= falling edge). interrupt request cause select register 2 bit name function bit symbol rw symbol address a fter reset ifsr2a 035e 16 00xxxxxx 2 b7 b6 b5 b4 b3 b2 b1 b0 aa aa a a aa aa aa aa 0 : timer b3 1 : uart0 bus collision detection 0 : timer b4 1 : uart1 bus collision detection ifsr26 ifsr27 interrupt request cause select bit interrupt request cause select bit rw rw (b5-b0) nothing is assigned. when write, set to 0. when read, their contents are indeterminate.
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r interrupts 90 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. interrupt control circuit kupic register key input interrupt request ki 3 ki 2 ki 1 ki 0 pur2 register's pu25 bit pd10 register's pd10_7 bit pull-up transistor pd10 register's pd10_7 bit pd10 register's pd10_6 bit pd10 register's pd10_5 bit pd10 register's pd10_4 bit pull-up transistor pull-up transistor pull-up transistor figure 1.11.11. key input interrupt ______ nmi interrupt _______ _______ ______ an nmi interrupt is generated when input on the nmi pin changes state from high to low. the nmi interrupt is a non-maskable interrupt. _______ the input level of this nmi interrupt input pin can be read by accessing the p8 registers p8_5 bit. this pin cannot be used as an input port. key input interrupt of p10 4 to p10 7 , a key input interrupt is generated when input on any of the p10 4 to p10 7 pins which has had the pd10 registers pd10_4 to pd10_7 bits set to 0 (= input) goes low. key input interrupts can be used as a key-on wakeup function, the function which gets the microcomputer out of wait or stop mode. however, if you intend to use the key input interrupt, do not use p10 4 to p10 7 as analog input ports. figure 1.11.11 shows the block diagram of the key input interrupt. note, however, that while input on any pin which has had the pd10_4 to pd10_7 bits set to 0 (= input mode) is pulled low, inputs on all other pins of the port are not detected as interrupts.
interrupts 91 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. address match interrupt an address match interrupt is generated immediately before executing the instruction at the address indi- cated by the rmadi register (i=0 to 3). set the start address of any instruction in the rmadi register. use the aier registers aier0 and aier1 bits and the aier2 registers aier20 and aier21 bits to enable or disable the interrupt. note that the address match interrupt is unaffected by the i flag and ipl. for address match interrupts, the value of the pc that is saved to the stack area varies depending on the instruction being executed. figure 1.11.12 shows the instruction just before execution and address stored in the stack when there occurs interruption. note that when using the external data bus in width of 8 bits, the address match interrupt cannot be used for external area. figure 1.11.13 shows the aier, aier2, and rmad0 to rmad3 registers. (1) instructions in which the "return destination + 2" address is stored in the stack when address match interrupt occurs ? 16-bit operation code ? instruction shown below among 8-bit operation code instructions add.b:s #imm8,dest sub.b:s #imm8,dest and.b:s #imm8,dest or.b:s #imm8,dest mov.b:s #imm8,dest stz.b:s #imm8,dest stnz.b:s #imm8,dest stzx.b:s #imm81,#imm82,dest cmp.b:s #imm8,dest pushm src popm dest jmps #imm8 jsrs #imm8 mov.b:s #imm,dest (however, dest = a0 or a1) (2) instructions in which the "return destination + 1" address is stored in the stack when address match interrupt occurs ? instructions other than the above figure 1.11.12. instruction just before execution and address stored in stack when there occurs interrupts table 1.11.6. relationship between address match interrupt sources and associated registers address match interrupt sources address match interrupt enable bit address match interrupt register address match interrupt 0 aier0 rmad0 address match interrupt 1 aier1 rmad1 address match interrupt 2 aier20 rmad2 address match interrupt 3 aier21 rmad3
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r interrupts 92 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. bit name bit symbol symbol address after reset aier 0009 16 xxxxxx00 2 address match interrupt enable register function rw aaaaaaaaaaaaaa aaaaaaaaaaaaaa aaaaaaaaaaaaaa aaaaaaaaaaaaaa address match interrupt 0 enable bit 0 : interrupt disabled 1 : interrupt enabled aier0 address match interrupt 1 enable bit aier1 symbol address after reset rmad0 0012 16 to 0010 16 x00000 16 rmad1 0016 16 to 0014 16 x00000 16 rmad2 01ba 16 to 01b8 16 x00000 16 rmad3 0 1be 16 to 01bc 16 x00000 16 b7 b6 b5 b4 b3 b2 b1 b0 address setting register for address match interrupt function setting range address match interrupt register i (i = 0 to 3) 00000 16 to fffff 16 0 : interrupt disabled 1 : interrupt enabled b0 b7 b0b3 (b19) (b16) b7 b0 (b15) (b8) b7 (b23) bit namebit symbol symbol address after reset aier2 01bb 16 xxxxxx00 2 address match interrupt enable register 2 function rw aaaaaaaaaaaaaa a aaaaaaaaaaaa a aaaaaaaaaaaaaa aaaaaaaaaaaaaa a aaaaaaaaaaaa a aaaaaaaaaaaaaa address match interrupt 2 enable bit 0 : interrupt disabled 1 : interrupt enabled aier20 address match interrupt 3 enable bit aier21 b7 b6 b5 b4 b3 b2 b1 b0 0 : interrupt disabled 1 : interrupt enabled rw rw (b7-b2) rw rw (b7-b2) rw rw nothing is assigned. when write, set to 0. when read, their contents are indeterminate. nothing is assigned. when write, set to 0. when read, their contents are indeterminate. nothing is assigned. when write, set to 0. when read, their contents are indeterminate. figure 1.11.13. aier register, aier2 register and rmad0 to rmad3 registers
interrupts 93 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. precautions for interrupts (1) reading address 00000 16 ? do not read the address 00000 16 in a program. when a maskable interrupt request is accepted, the cpu reads interrupt information (interrupt number and interrupt request priority level) from the address 00000 16 during the interrupt sequence. at this time, the ir bit for the accepted interrupt is cleared to 0. if the address 00000 16 is read in a program, the ir bit for the interrupt which has the highest priority among the enabled interrupts is cleared to 0. this causes a problem that the interrupt is canceled, or an unexpected interrupt is generated. (2) sp setting ? set any value in the sp before accepting an interrupt. the sp is cleared to 0000 16 after reset. there- fore, if an interrupt is accepted before setting any value in the sp, the program may go out of control. _______ especially when using nmi interrupt, set a value in the sp at the beginning of the program. for the first _______ and only the first instruction after reset, all interrupts including nmi interrupt are disabled. _______ (3) nmi interrupt _______ _______ ? the nmi interrupt cannot be disabled. if this interrupt is unused, connect the nmi pin to v cc via a resistor (pull-up). _______ ? the input level of the nmi pin can be read by accessing the p8 registers p8_5 bit. note that the p8_5 bit _______ can only be read when determining the pin level after an nmi interrupt is generated. _______ ? stop mode cannot be entered into while input on the nmi pin is low. this is because while input on the _______ nmi pin is low the cm1 registers cm10 bit is fixed to 0. _______ _______ ? do not go to wait mode while input on the nmi pin is low. this is because when input on the nmi pin goes low, the cpu stops but cpu clock remains active; therefore, the current consumption in the chip does not drop. in this case, normal condition is restored by an interrupt generated thereafter. _______ ? the low and high level durations of the input signal to the nmi pin must each be 2 cpu clock cycles + 300 ns or more. _____ (4) int interrupt ________ ? either an l level or an h level of at least 250 ns width is necessary for the signal input to the int 0 ________ through int 5 pins regardless of the cpu clock. ________ ________ ? when the polarity of the int 0 to int 5 pins is changed, the ir bit is sometimes set to 1 (=interrupt requested). after changing the polarity, set the ir bit to 0 (=interrupt not requested). figure 1.11.13 ______ shows the procedure for changing the int interrupt generate factor. ______ figure 1.11.14. switching procedure for int interrupt request set the ilvl2 to ilvl0 bits to '000 2 ' (= level 0) (disable int interrupt) set the pol bit set the ilvl2 to ilvl0 bits to '001 2 ' (=level 1) to '111 2 ' (=level 7) (enable the accepting of int interrupt request) set the i flag to 0 (=disable interrupt) set the i flag to 1 (= enable interrupt) note: execute the setting above individually. do not execute two or more settings at once (by one instruction). set the ir bit to 0 (=interrupt not requested)
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r interrupts 94 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. example 1: int_switch1: fclr i ; disable interrupts. and.b #00h, 0055h ; set the ta0ic register to 00 16 . nop ; four nop instructions are required when using hold function. nop fset i ; enable interrupts. example 2: int_switch2: fclr i ; disable interrupts. and.b #00h, 0055h ; set the ta0ic register to 00 16 . mov.w mem, r0 ; dummy read. fset i ; enable interrupts. example 3: int_switch3: pushc flg ; push flag register onto stack fclr i ; disable interrupts. and.b #00h, 0055h ; set the ta0ic register to 00 16 . popc flg ; enable interrupts. why the fset i instruction is preceded by two nop instructions (four when using hold function) in example 1 and why the fset i instruction is preceded by a dummy read in example 2 this is to prevent the i flag from being set to 1 before writing to the interrupt control register for reasons of the instruction queue buffer. (5) watchdog timer interrupt ? initialize the watchdog timer after the watchdog timer interrupt occurs. (6) modifying interrupt control register ? each interrupt control register can only be modified while no interrupt requests corresponding to that register are generated. if interrupt requests managed by any interrupt control register are likely to occur, disable the interrupts before modifying the register. a sample program is shown below. to modify any interrupt control register after disabling interrupts, be careful with the instructions used. modifying other than the ir bit if an interrupt request corresponding to that register is generated while executing the instruction, the ir bit may not be set to 1 (= interrupt requested), with the result that the interrupt request is ignored. if this presents a problem, use the following instructions to modify the register. instructions to use: and, or, bclr, bset modifying the ir bit even when the ir bit is cleared to 0 (= interrupt not requested), it may not actually be cleared to 0 depending on the instruction used. therefore, use the mov instruction to clear the ir bit.
watchdog timer 95 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. watchdog timer the watchdog timer is the function of detecting when the program is out of control. therefore, we recom- mend using the watchdog timer to improve reliability of a system. the watchdog timer contains a 15-bit counter which counts down the clock derived by dividing the cpu clock using the prescaler. whether to generate a watchdog timer interrupt request or apply a watchdog timer reset as an operation to be per- formed when the watchdog timer underflows after reaching the terminal count can be selected using the pm12 bit of pm1 register. the pm12 bit can only be set to 1 (reset). once this bit is set to 1, it cannot be set to 0 (watchdog timer interrupt) in a program. the pin, cpu and sfr initialized where the monitor timer underflows when the pm12 bit is 1 are the same as in software reset. when the main clock is selected for cpu clock, the divide-by-n value for the prescaler can be chosen to be 16 or 128. if a sub-clock is selected for cpu clock, the divide-by-n value for the prescaler is always 2 no matter how the wdc7 bit is set. the period of watchdog timer can be calculated as given below. the period of watchdog timer is, however, subject to an error due to the prescaler. for example, when cpu clock = 16 mhz and the divide-by-n value for the prescaler= 16, the watchdog timer period is approx. 32.8 ms. the watchdog timer is initialized by writing to the wdts register. the prescaler is initialized after reset. note that the watchdog timer and the prescaler both are inactive after reset, so that the watchdog timer is activated to start counting by writing to the wdts register. in stop mode, wait mode and hold state, the watchdog timer and prescaler are stopped. counting is re- sumed from the held value when the modes or state are released. figure 1.12.1 shows the block diagram of the watchdog timer. figure 1.12.2 shows the watchdog timer- related registers. ? count source protective mode in this mode, a ring oscillator clock is used for the watchdog timer count source. the watchdog timer can be kept being clocked even when cpu clock stops as a result of run-away. before this mode can be used, the following register settings are required: (1) set the prc1 bit of prcr register to 1 (enable writes to pm1 and pm2 registers). (2) set the pm12 bit of pm1 register to 1 (reset when the watchdog timer underflows). (3) set the pm22 bit of pm2 register to 1 (ring oscillator clock used for the watchdog timer count source). (4) set the prc1 bit of prcr register to 0 (disable writes to pm1 and pm2 registers). (5) write to the wdts register (watchdog timer starts counting). with main clock chosen for cpu clock watchdog timer period = prescaler dividing (16 or 128) x watchdog timer count (32768) cpu clock with sub-clock chosen for cpu clock watchdog timer period = prescaler dividing (2) x watchdog timer count (32768) cpu clock
watchdog timer 96 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. watchdog timer start register (note) symbol address after reset wdts 000e 16 indeterminate wo b7 b0 function the watchdog timer is initialized and starts counting after a write instruction to this register. the watchdog timer value is always initialized to 7fff 16 regardless of whatever value is written. rw note : write to the wdts register after the watchdog timer interrupt occurs. figure 1.12.2. wdc register and wdts register cpu clock write to wdts register reset pm12 = 0 watchdog timer set to 7fff 16 1/128 1/16 cm07 = 0 wdc7 = 1 cm07 = 0 wdc7 = 0 cm07 = 1 hold 1/2 prescaler pm12 = 1 watchdog timer interrupt request reset pm22 = 0 pm22 = 1 ring oscillator clock figure 1.12.1. watchdog timer block diagram watchdog timer control register symbol address a fter reset wdc 000f 16 00xxxxxx 2 (note2) function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 high-order bit of watchdog timer wdc7 bit name prescaler select bit 0 : divided by 16 1 : divided by 128 reserved bit m ust set to 0 0 ro rw rw rw cold start / warm start discrimination flag (note 1) 0 : cold start 1 : warm start wdc5 note 1: the wdc5 bit is always 1 (warm start) no matter how it is set by writing a 0 or 1. note 2: the wdc5 bit is 0 (cold start) immediately after power-on. it can only be set to 1 in a program. it is set to 0 when the input voltage at the v cc1 pin drops to v det 2 or less while the vc25 bit in the vcr2 register is set to 1 (ram retention limit detection circuit enable). (b4-b0) (b6) setting the pm22 bit to 1 results in the following conditions ? the ring oscillator starts oscillating, and the ring oscillator clock becomes the watchdog timer count source. ? the cm10 bit of cm1 register is disabled against write. (writing a 1 has no effect, nor is stop mode entered.) ? the watchdog timer does not stop when in wait mode or hold state.
dmac 97 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. dmac the dmac (direct memory access controller) allows data to be transferred without the cpu intervention. two dmac channels are included. each time a dma request occurs, the dmac transfers one (8 or 16-bit) data from the source address to the destination address. the dmac uses the same data bus as used by the cpu. because the dmac has higher priority of bus control than the cpu and because it makes use of a cycle steal method, it can transfer one word (16 bits) or one byte (8 bits) of data within a very short time after a dma request is generated. figure 1.13.1 shows the block diagram of the dmac. table 1.13.1 shows the dmac specifications. figures 1.13.2 to 1.13.4 show the dmac-related registers. figure 1.13.1. dmac block diagram a a a a a a aa aa aa aa a a aa aa aa aa aa a a a a a a data bus low-order bits dma latch high-order bits dma latch low-order bits dma0 source pointer sar0(20) dma0 destination pointer dar0 (20) dma0 forward address pointer (20) (note) data bus high-order bits aa aa aa aa a a aa aa aaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaa aaaaaaa address bus a a a a a a aa aa dma1 destination pointer dar1 (20) dma1 source pointer sar1 (20) dma1 forward address pointer (20) (note) aa aa aa dma0 transfer counter reload register tcr0 (16) dma0 transfer counter tcr0 (16) dma1 transfer counter reload register tcr1 (16) dma1 transfer counter tcr1 (16) a a (addresses 0029 16 , 0028 16 ) (addresses 0039 16 , 0038 16 ) (addresses 0022 16 to 0020 16 ) (addresses 0026 16 to 0024 16 ) (addresses 0032 16 to 0030 16 ) (addresses 0036 16 to 0034 16 ) note: pointer is incremented by a dma request. aa aa aa aa aa aa a a a a a a a a a a aa aa aa aa a a a a a a a a a a dma request is generated by a write to the dmisl register (i = 0e1)?s dsr bit, as well as by an interrupt request which is generated by any function specified by the dmisl register?s dms and dsel3edsel0 bits. however, unlike in the case of interrupt requests, dma requests are not affected by the i flag and the interrupt control register, so that even when interrupt requests are disabled and no interrupt request can be accepted, dma requests are always accepted. furthermore, because the dmac does not affect interrupts, the interrupt control register?s ir bit does not change state due to a dma transfer. a data transfer is initiated each time a dma request is generated when the dmicon register?s dmae bit = 1 (dma enabled). however, if the cycle in which a dma request is generated is faster than the dma transfer cycle, the number of transfer requests generated and the number of times data is transferred may not match. for details, refer to dma requests.
dmac 98 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. item specification no. of channels 2 (cycle steal method) transfer memory space ? from any address in the 1m bytes space to a fixed address ? from a fixed address to any address in the 1m bytes space ? from a fixed address to a fixed address maximum no. of bytes transferred 128k bytes (with 16-bit transfers) or 64k bytes (with 8-bit transfers) dma request factors ________ ________ falling edge of int0 or int1 (note 1, note 2) ________ ________ both edge of int0 or int1 timer a0 to timer a4 interrupt requests timer b0 to timer b5 interrupt requests uart0 transfer, uart0 reception interrupt requests uart1 transfer, uart1 reception interrupt requests uart2 transfer, uart2 reception interrupt requests si/o3, si/o4 interrpt requests a-d conversion interrupt requests software triggers channel priority dma0 > dma1 (dma0 takes precedence) transfer unit 8 bits or 16 bits transfer address direction forward or fixed (the source and destination addresses cannot both be in the forward direction.) transfer mode ?single transfer transfer is completed when the dmai transfer counter (i = 0C1) underflows after reaching the terminal count. ?repeat transfer when the dmai transfer counter underflows, it is reloaded with the value of the dmai transfer counter reload register and a dma transfer is con tinued with it. dma interrupt request generation timing when the dmai transfer counter underflowed dma startup data transfer is initiated each time a dma request is generated when the dmaicon registers dmae bit = 1 (enabled). dma shutdown ?single transfer ? when the dmae bit is set to 0 (disabled) ? after the dmai transfer counter underflows ?repeat transfer when the dmae bit is set to 0 (disabled) when a data transfer is started after setting the dmae bit to 1 (en abled), the forward address pointer is reloaded with the value of the sari or the dari pointer whichever is specified to be in the forward direction and the dmai transfer counter is reloaded with the value of the dmai transfer counter reload register. table 1.13.1. dmac specifications notes: 1. dma transfer is not effective to any interrupt. dma transfer is affected neither by the i flag nor by the interrupt control register. 2. the selectable causes of dma requests differ with each channel. 3. make sure that no dmac-related registers (addresses 0020 16 C003f 16 ) are accessed by the dmac. reload timing for forward ad- dress pointer and transfer counter
dmac 99 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. dma0 request cause select register symbol address after reset dm0sl 03b8 16 00 16 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 dma request cause select bit dsel0 rw dsel1 dsel2 dsel3 nothing is assigned. when write, set to 0. when read, its content is 0. software dma request bit a dma request is generated by setting this bit to 1 when the dms bit is 0 (basic cause) and the dsel3 to dsel0 bits are 0001 2 (software trigger). the value of this bit when read is 0 . dsr dsel3 to dsel0 dms=0(basic cause of request) dms=1(extended cause of request) 0 0 0 0 2 falling edge of int0 pin C 0 0 0 1 2 software trigger C 0 0 1 0 2 timer a0 C 0 0 1 1 2 timer a1 C 0 1 0 0 2 timer a2 C 0 1 0 1 2 timer a3 C 0 1 1 0 2 timer a4 two edges of int0 pin 0 1 1 1 2 timer b0 timer b3 1 0 0 0 2 timer b1 timer b4 1 0 0 1 2 timer b2 timer b5 1 0 1 0 2 uart0 transmit C 1 0 1 1 2 uart0 receive C 1 1 0 0 2 uart2 transmit C 1 1 0 1 2 uart2 receive C 1 1 1 0 2 a-d conversion C 1 1 1 1 2 uart1 transmit C bit name dma request cause expansion select bit dms 0: basic cause of request 1: extended cause of request rw rw rw rw rw rw (b5-b4) refer to note note: the causes of dma0 requests can be selected by a combination of dms bit and dsel3 to dsel0 bits in the manner described below. figure 1.13.2. dm0sl register
dmac 100 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. dmai control register (i=0,1) symbol address after reset dm0con 002c 16 00000x00 2 dm1con 003c 16 00000x00 2 bit name function bit symbol transfer unit bit select bit b7 b6 b5 b4 b3 b2 b1 b0 0 : 16 bits 1 : 8 bits dmbit dmasl dmas dmae repeat transfer mode select bit 0 : single transfer 1 : repeat transfer dma request bit 0 : dma not requested 1 : dma requested 0 : disabled 1 : enabled 0 : fixed 1 : forward dma enable bit source address direction select bit (note 2) destination address direction select bit (note 2) 0 : fixed 1 : forward dsd dad nothing is assigned. when write, set to 0. when read, its content is 0. note 1: the dmas bit can be set to 0 by writing 0 in a program (this bit remains unchanged even if 1 is written). note 2: at least one of the dad and dsd bits must be 0 ( address direction fixed ) . (note 1) dma1 request cause select register symbol address after reset dm1sl 0 3ba 16 00 16 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 dma request cause select bit dsel0 rw dsel1 dsel2 dsel3 software dma request bit dsr dsel3 to dsel0 dms=0(basic cause of request) dms=1(extended cause of request) 0 0 0 0 2 falling edge of int1 pin C 0 0 0 1 2 software trigger C 0 0 1 0 2 timer a0 C 0 0 1 1 2 timer a1 C 0 1 0 0 2 timer a2 C 0 1 0 1 2 timer a3 si/o3 0 1 1 0 2 timer a4 si/o4 0 1 1 1 2 timer b0 two edges of int1 1 0 0 0 2 timer b1 C 1 0 0 1 2 timer b2 C 1 0 1 0 2 uart0 transmit C 1 0 1 1 2 uart0 receive/ack0 C 1 1 0 0 2 uart2 transmit C 1 1 0 1 2 uart2 receive/ack2 C 1 1 1 0 2 a-d conversion C 1 1 1 1 2 uart1 receive/ack1 C bit name dma request cause expansion select bit dms rw rw rw rw rw rw (b5-b4) rw rw rw rw rw rw rw (b7-b6) note: the causes of dma1 requests can be selected by a combination of dms bit and dsel3 to dsel0 bits in the manner described below. nothing is assigned. when write, set to 0. when read, its content is 0. a dma request is generated by setting this bit to 1 when the dms bit is 0 (basic cause) and the dsel3 to dsel0 bits are 0001 2 (software trigger). the value of this bit when read is 0 . 0: basic cause of request 1: extended cause of request refer to note figure 1.13.3. dm1sl register, dm0con register, and dm1con registers
dmac 101 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. b7 b0 b7 b0 (b8)(b15) function set the transfer count minus 1. the written value is stored in the dmai transfer counter reload register, and when the dmae bit of dmicon register is set to 1 (dma enabled) or the dmai transfer counter underflows when the dmasl bit of dmicon register is 1 (repeat transfer), the value of the dmai transfer counter reload register is transferred to the dmai transfer counter. when read, the dmai transfer counter is read. symbol address after reset tcr0 0029 16 , 0028 16 indeterminate tcr1 0039 16 , 0038 16 indeterminate dmai transfer counter (i = 0, 1) setting range 0000 16 to ffff 16 b7 (b23) b3 b0 b7 b0 b7 b0 (b8)(b16)(b15)(b19) function rw set the source address of transfer symbol address a fter reset sar0 0022 16 to 0020 16 indeterminate sar1 0032 16 to 0030 16 indeterminate dmai source pointer (i = 0, 1) (note) setting range 00000 16 to fffff 16 nothing is assigned. when write, set 0. when read, these contents are 0. symbol address after reset dar0 0026 16 to 0024 16 indeterminate dar1 0036 16 to 0034 16 indeterminate b3 b0 b7 b0 b7 b0 (b8)(b15)(b16)(b19) function set the destination address of transfer dmai destination pointer (i = 0, 1)(note) setting range 00000 16 to fffff 16 b7 (b23) rw rw rw rw rw note: if the dsd bit of dmicon register is 0 (fixed), this register can only be written to when the dmae bit of dmicon register is 0 (dma disabled). if the dsd bit is 1 (forward direction), this register can be written to at any time. if the dsd bit is 1 and the dmae bit is 1 (dma enabled), the dmai forward address pointer can be read from this register. otherwise, the value written to it can be read. nothing is assigned. when write, set 0. when read, these contents are 0. note: if the dad bit of dmicon register is 0 (fixed), this register can only be written to when the dmae bit of dmicon register is 0(dma disabled). if the dad bit is 1 (forward direction), this register can be written to at any time. if the dad bit is 1 and the dmae bit is 1 (dma enabled), the dmai forward address pointer can be read from this register. otherwise, the value written to it can be read. figure 1.13.4. sar0, sar1, dar0, dar1, tcr0, and tcr1 registers
dmac 102 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. 1. transfer cycles the transfer cycle consists of a memory or sfr read (source read) bus cycle and a write (destination write) bus cycle. the number of read and write bus cycles is affected by the source and destination addresses of transfer. during memory extension and microprocessor modes, it is also affected by the ________ byte pin level. furthermore, the bus cycle itself is extended by a software wait or rdy signal. (a) effect of source and destination addresses if the transfer unit and data bus both are 16 bits and the source address of transfer begins with an odd address, the source read cycle consists of one more bus cycle than when the source address of transfer begins with an even address. similarly, if the transfer unit and data bus both are 16 bits and the destination address of transfer begins with an odd address, the destination write cycle consists of one more bus cycle than when the destination address of transfer begins with an even address. (b) effect of byte pin level during memory extension and microprocessor modes, if 16 bits of data are to be transferred on an 8- bit data bus (input on the byte pin = high), the operation is accomplished by transferring 8 bits of data twice. therefore, this operation requires two bus cycles to read data and two bus cycles to write data. furthermore, if the dmac is to access the internal area (internal rom, internal ram, or sfr), unlike in the case of the cpu, the dmac does it through the data bus width selected by the byte pin. (c) effect of software wait for memory or sfr accesses in which one or more software wait states are inserted, the number of bus cycles required for that access increases by an amount equal to software wait states. _______ (d) effect of rdy signal during memory extension and microprocessor modes, dma transfers to and from an external area ________ ________ are affected by the rdy signal. refer to rdy signal. figure 1.13.5 shows the example of the cycles for a source read. for convenience, the destination write cycle is shown as one cycle and the source read cycles for the different conditions are shown. in reality, the destination write cycle is subject to the same conditions as the source read cycle, with the transfer cycle changing accordingly. when calculating transfer cycles, take into consideration each condition for the source read and the destination write cycle, respectively. for example, when data is transferred in 16 bit units using an 8-bit bus ((2) in figure 1.13.5), two source read bus cycles and two destination write bus cycles are required.
dmac 103 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. bclk address bus rd signal wr signal data bus cpu use cpu use cpu use cpu use source source destination destination dummy cycle dummy cycle (1) when the transfer unit is 8 or 16 bits and the source of transfer is an even address bclk address bus rd signal wr signal data bus cpu use cpu use cpu use cpu use source source destination destination dummy cycle dummy cycle (3) when the source read cycle under condition (1) has one wait state inserted bclk address bus rd signal wr signal data bus cpu use cpu use cpu use cpu use source source destination destination dummy cycle dummy cycle source + 1 source + 1 (2) when the transfer unit is 16 bits and the source address of transfer is an odd address, or when the transfer unit is 16 bits and an 8-bit bus is used bclk address bus rd signal wr signal data bus cpu use cpu use cpu use cpu use source source destination destination dummy cycle dummy cycle source + 1 source + 1 (4) when the source read cycle under condition (2) has one wait state inserted note: the same timing changes occur with the respective conditions at the destination as at the source. figure 1.13.5. transfer cycles for source read
dmac 104 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. single-chip mode memory expansion mode transfer unit bus width access address microprocessor mode no. of read no. of write no. of read no. of write cycles cycles cycles cycles 16-bit even 1 1 1 1 8-bit transfers (byte= l) odd 1 1 1 1 (dmbit= 1) 8-bit even 1 1 (byte = h) odd 1 1 16-bit even 1 1 1 1 16-bit transfers (byte = l) odd 2 2 2 2 (dmbit= 0) 8-bit even 2 2 (byte = h) odd 2 2 table 1.13.2. dma transfer cycles 2. dma transfer cycles any combination of even or odd transfer read and write addresses is possible. table 1.13.2 shows the number of dma transfer cycles. table 1.13.3 shows the coefficient j, k. the number of dmac transfer cycles can be calculated as follows: no. of transfer cycles per transfer unit = no. of read cycles x j + no. of write cycles x k table 1.13.3. coefficient j, k internal area internal rom, ram s fr separate bus external area multiplex bus no wait with wait no wait with wait 1 1 1 2 2 3 3 1 2 1 wait 2 2 waits 3 3 waits 4 1wait 3 2 waits 3 3 waits 4 with wait 1 j k 2 3 433 4 notes: 1. depends on the set value of cse register. 2. depends on the set value of pm20 bit in pm2 register. 2 2 1-wait 2 2-wait 2
dmac 105 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. 3. dma enable when a data transfer starts after setting the dmae bit in dmicon register (i = 0, 1) to 1 (enabled), the dmac operates as follows: (1) reload the forward address pointer with the sari register value when the dsd bit in dmicon register is 1 (forward) or the dari register value when the dad bit of dmicon register is 1 (forward). (2) reload the dmai transfer counter with the dmai transfer counter reload register value. if the dmae bit is set to 1 again while it remains set, the dmac performs the above operation. however, if a dma request may occur simultaneously when the dmae bit is being written, follow the steps below. step 1: write 1 to the dmae bit and dmas bit in dmicon register simultaneously. step 2: make sure that the dmai is in an initial state as described above (1) and (2) in a program. if the dmai is not in an initial state, the above steps should be repeated. 4. dma request the dmac can generate a dma request as triggered by the cause of request that is selected with the dms and dsel3 to dsel0 bits of dmisl register (i = 0, 1) on either channel. table 1.13.4 shows the timing at which the dmas bit changes state. whenever a dma request is generated, the dmas bit is set to 1 (dma requested) regardless of whether or not the dmae bit is set. if the dmae bit was set to 1 (enabled) when this occurred, the dmas bit is set to 0 (dma not requested) immediately before a data transfer starts. this bit cannot be set to 1 in a program (it can only be set to 0). the dmas bit may be set to 1 when the dms or the dsel3 to dsel0 bits change state. therefore, always be sure to set the dmas bit to 0 after changing the dms or the dsel3 to dsel0 bits. because if the dmae bit is 1, a data transfer starts immediately after a dma request is generated, the dmas bit in almost all cases is 0 when read in a program. read the dmae bit to determine whether the dmac is enabled. table 1.13.4. timing at which the dmas bit changes state dma factor software trigger peripheral function timing at which the bit is set to 1 timing at which the bit is set to 0 dmas bit of the dmicon register when the dsr bit of dmicon register is set to 1 when the interrupt control register for the peripheral function that is selected by the dsel3 to dsel0 and dms bits of dmicon register has its ir bit set to 1 ? immediately before a data transfer starts ? when set by writing 0 in a program
dmac 106 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. channel priority and dma transfer timing if both dma0 and dma1 are enabled and dma transfer request signals from dma0 and dma1 are detected active in the same sampling period (one period from a falling edge to the next falling edge of bclk), the dmas bit on each channel is set to 1 (dma requested) at the same time. in this case, the dma requests are arbitrated according to the channel priority, dma0 > dma1. the following describes dmac operation when dma0 and dma1 requests are detected active in the same sampling period. figure 1.13.6 shows an example of dma transfer effected by external factors. in figure 1.13.6, because dma0 and dma1 requests occurred at the same time, dma0 which has higher channel priority is accepted first and a dma transfer on it starts. when dma0 finishes one transfer unit, it relinquishes control of the bus to the cpu, and when the cpu finishes one bus access, dma1 starts a transfer next and after completion of one transfer unit, returns control of the bus to the cpu. note that because there is only one dmas bit on each channel, the number of times dma is requested cannot be counted. therefore, even if multiple dma requests occurred before gaining control of the bus as in the case of dma1 in figure 1.13.6, the dmas bit is set to 0 when control of the bus is gained and after completion of one transfer unit, control of the bus is returned to the cpu. bclk aaaa aaaa dma0 aaaa aaaa dma1 dma0 request bit dma1 request bit aaa aaaaaa a a aaaaaa aa cpu int0 int1 obtainment of the bus right an example where dma requests for external causes are detected active at the same figure 1.13.6. dma transfer by external factors
timers 107 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. timers eleven 16-bit timers, each capable of operating independently of the others, can be classified by function as either timer a (five) and timer b (six). the count source for each timer acts as a clock, to control such timer operations as counting, reloading, etc. figures 1.14.1 and 1.14.2 show block diagrams of timer a and timer b configuration, respectively. ? timer mode ? one-shot timer mode ? pulse width measuring (pwm) mode ? timer mode ? one-shot timer mode ? pwm mode ? timer mode ? one-shot timer mode ? pwm mode ? timer mode ? one-shot timer mode ? pwm mode ? timer mode ? one-shot timer mode ? pwm mode ? event counter mode ? event counter mode ? event counter mode ? event counter mode ? event counter mode ta0 in ta1 in ta2 in ta3 in ta4 in timer a0 timer a1 timer a2 timer a3 timer a4 f 8 f 32 f c32 timer a0 interrupt timer a1 interrupt timer a2 interrupt timer a3 interrupt timer a4 interrupt noise filter noise filter noise filter noise filter noise filter 1/32 f c32 1/8 1/4 f 1 or f 2 f 8 f 32 ? main clock ? pll clock ? ring oscillator clock x cin set the cpsr bit of cpsrf register to 1 (= prescaler reset) reset clock prescaler timer b2 overflow or underflow note: be aware that ta0 in shares the pin with rxd 2 and tb5 in . 1/2 f 1 f 2 pclk0 bit = 0 pclk0 bit = 1 f 1 or f 2 figure 1.14.1. timer a configuration
timers 108 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.14.2. timer b configuration ? event counter mode ? event counter mode ? event counter mode ? timer mode ? pulse width measuring mode, pulse period measuring mode ? timer mode ? pulse width measuring mode, pulse period measuring mode ? timer mode ? pulse width measuring mode, pulse period measuring mode tb0 in tb1 in tb2 in timer b0 timer b1 timer b2 f 8 f 32 f c32 timer b0 interrupt noise filter noise filter noise filter 1/32 f c32 x cin reset clock prescaler timer b2 overflow or underflow ( to timer a count source) ? event counter mode ? event counter mode ? event counter mode ? timer mode ? pulse width measuring mode, pulse period measuring mode ? timer mode ? pulse width measuring mode, pulse period measuring mode ? timer mode ? pulse width measuring mode, pulse period measuring mode tb3 in tb4 in tb5 in timer b3 timer b4 timer b5 timer b3 interrupt noise filter noise filter noise filter timer b1 interrupt timer b2 interrupt timer b4 interrupt timer b5 interrupt 1/8 1/4 f 8 f 32 1/2 f 1 or f 2 ? main clock ? pll clock ? ring oscillator clock set the cpsr bit of cpsrf register to 1 (= prescaler reset) note: be aware that tb5 in shares the pin with rxd 2 and ta0 in . f 1 f 2 pclk0 bit = 0 pclk0 bit = 1 f 1 or f 2
timers (timer a) 109 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. timer a figure 1.14.3 shows a block diagram of the timer a. figures 1.14.4 to 1.14.6 show registers related to the timer a. the timer a supports the following four modes. except in event counter mode, timers a0 to a4 all have the same function. use the tmod1 to tmod0 bits of taimr register (i = 0 to 4) to select the desired mode. ? timer mode: the timer counts an internal count source. ? event counter mode: the timer counts pulses from an external device or overflows and underflows of other timers. ? one-shot timer mode: the timer outputs a pulse only once before it reaches the minimum count 0000 16 . ? pulse width modulation (pwm) mode: the timer outputs pulses in a given width successively. figure 1.14.4. ta0mr to ta4mr registers tabsr register up-count/down-count tai addresses taj tak timer a0 0387 16 0386 16 timer a4 timer a1 timer a1 0389 16 0388 16 timer a0 timer a2 timer a2 038b 16 038a 16 timer a1 timer a3 timer a3 038d 16 038c 16 timer a2 timer a4 timer a4 038f 16 038e 16 timer a3 timer a0 always counts down except in event counter mode reload register counter low-order 8 bits aaaa high-order 8 bits clock source selection timer (gate function) timer one shot pwm f 1 or f 2 f 8 f 32 tai in (i = 0 to 4) tb2 overflow event counter f c32 clock selection taj overflow (j = i e 1. note, however, that j = 4 when i = 0) pulse output toggle flip-flop tai out (i = 0 to 4) data bus low-order bits data bus high-order bits a a udf register down count tak overflow (k = i + 1. note, however, that k = 0 when i = 4) polarity selection to external trigger circuit (note) (note) note: overflow or underflow clock selection timer ai mode register (i=0 to 4) symbol address after reset ta0mr to ta4mr 0396 16 to 039a 16 00 16 bit name functionbit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 0 0 : timer mode 0 1 : event counter mode 1 0 : one-shot timer mode 1 1 : pulse width modulation (pwm) mode b1 b0 tck1 mr3 mr2 mr1 tmod1 mr0 tmod0 tck0 function varies with each operation mode count source select bit operation mode select bit rw rw rw rw rw rw rw rw function varies with each operation mode figure 1.14.3. timer a block diagram
timers (timer a) 110 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.14.5. ta0 to ta4 registers, tabsr register, and udf register symbol address a fter reset ta0 0387 16 , 0386 16 indeterminate ta1 0389 16 , 0388 16 indeterminate ta2 038b 16 , 038a 16 indeterminate ta3 038d 16 , 038c 16 indeterminate ta4 038f 16 , 038e 16 indeterminate b7 b0 b7 b0 (b15) (b8) timer ai register (i= 0 to 4) (note 1) rw divide the count source by n + 1 where n = set value function setting range divide the count source by ffff 16 C n + 1 where n = set value when counting up or by n + 1 when counting down divide the count source by n where n = set value and cause the timer to stop modify the pulse width as follows: pwm period: (2 16 C 1) / fj high level pwm pulse width: n / fj where n = set value, fj = count source frequency 0000 16 to fffe 16 (note 3, 4) note 1: the register must be accessed in 16 bit units. note 2: if the tai register is set to 0000 16 , the counter does not work and timer ai interrupt requests are not generated either. furthermore, if pulse output is selected, no pulses are output from the taiout pin. note 3: if the tai register is set to 0000 16 , the pulse width modulator does not work, the output level on the taiout pin remains low, and timer ai interrupt requests are not generated either. the same applies when the 8 high-order bits of the timer tai register are set to 001 6 while operating as an 8-bit pulse width modulator. note 4: use the mov instruction to write to the tai register. note 5: the timer counts pulses from an external device or overflows or underflows in other timers. 00 16 to fe 16 (high-order address) 00 16 to ff 16 (low-order address) timer a4 up/down flag timer a3 up/down flag timer a2 up/down flag timer a1 up/down flag timer a0 up/down flag timer a2 two-phase pulse signal processing select bit timer a3 two-phase pulse signal processing select bit timer a4 two-phase pulse signal processing select bit symbol address a fter reset udf 0384 16 00 16 ta4p ta3p ta2p up/down flag (note 1) bit name functionbit symbol b7 b6 b5 b4 b3 b2 b1 b0 ta4ud ta3ud ta2ud ta1ud ta0ud 0 : down count 1 : up count enabled by setting the taimr registers mr2 bit to 0 (= switching source in udf register) during event counter mode. 0 : two-phase pulse signal processing disabled 1 : two-phase pulse signal processing enabled symbol address a fter reset tabsr 0380 16 00 16 count start flag bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 aaaaaaaaaaaaaa aaaaaaaaaaaaaa aaaaaaaaaaaaaa aaaaaaaaaaaaaa aaaaaaaaaaaaaa timer b2 count start flag timer b1 count start flag timer b0 count start flag timer a4 count start flag timer a3 count start flag timer a2 count start flag timer a1 count start flag timer a0 count start flag 0 : stops counting 1 : starts counting tb2s tb1s tb0s ta4s ta3s ta2s ta1s ta0s note 1: use mov instruction to write to this register. note 2: make sure the port direction bits for the ta2 in to ta4i n and ta2 out to ta4 out pins are set to 0 (input mode). note 3: when not using the two-phase pulse signal processing function, set the corresponding bit to 0. rw rw wo wo wo rw rw rw rw rw rw rw rw rw rw rw rw rw rw wo wo wo timer mode event counter mode one-shot timer mode pulse width modulation mode (16-bit pwm) pulse width modulation mode (8-bit pwm) 0000 16 to ffff 16 0000 16 to ffff 16 0000 16 to ffff 16 (notes 2, 4) mode modify the pulse width as follows: pwm period: (2 8 e 1) x (m + 1)/ fj high level pwm pulse width: (m + 1)n / fj where n = high-order address set value, m = low-order address set value, fj = count source frequency (note 3, 4) (notes 2, 3) (note 5)
timers (timer a) 111 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. symbol address after reset cpsrf 0381 16 0xxxxxxx 2 clock prescaler reset flag bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa clock prescaler reset flag setting this bit to 1 initializes the prescaler for the timekeeping clock. ( when read, its content is 0.) cpsr nothing is assigned. when write, set to 0. when read, their contents are indeterminate. ta1tgl symbol address a fter reset trgsr 0383 16 00 16 timer a1 event/trigger select bit 0 0 : input on ta1 in is selected (note 1) 0 1 : tb2 overflow is selected 1 0 : ta0 overflow is selected 1 1 : ta2 overflow is selected trigger select register bit name functionbit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0 : input on ta2 in is selected (note 1) 0 1 : tb2 overflow is selected 1 0 : ta1 overflow is selected 1 1 : ta3 overflow is selected 0 0 : input on ta3 in is selected (note 1) 0 1 : tb2 overflow is selected 1 0 : ta2 overflow is selected 1 1 : ta4 overflow is selected 0 0 : input on ta4 in is selected (note 1) 0 1 : tb2 overflow is selected 1 0 : ta3 overflow is selected 1 1 : ta0 overflow is selected timer a2 event/trigger select bit timer a3 event/trigger select bit timer a4 event/trigger select bit ta1tgh ta2tgl ta2tgh ta3tgl ta3tgh ta4tgl ta4tgh b1 b0 b3 b2 b5 b4 b7 b6 note 1: make sure the port direction bits for the ta1 in to ta4 in pins are set to 0 (= input mode). note 2: overflow or underflow ta1os ta2os ta0os one-shot start flag symbol address after reset onsf 0382 16 00 16 timer a0 one-shot start flag timer a1 one-shot start flag timer a2 one-shot start flag timer a3 one-shot start flag timer a4 one-shot start flag ta3os ta4os bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 ta0tgl ta0tgh 0 0 : input on ta0 in is selected 0 1 : tb2 overflow is selected 1 0 : ta4 overflow is selected 1 1 : ta1 overflow is selected timer a0 event/trigger select bit b7 b6 rw the timer starts counting by setting this bit to 1 while the tmod1 to tmod0 bits of taimr register (i = 0 to 4) = ?10 2 ? (= one-shot timer mode) and the mr2 bit of taimr register = 0 (=taios bit enabled). when read, its content is 0. z-phase input enable bit ta4os 0 : z-phase input disabled 1 : z-phase input enabled rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw (b6-b0) (note 2) (note 2) (note 2) (note 2) (note 2) (note 2) (note 2) (note 2) (note 2) (note 2) (note 2) (note 2) (note 2) (note 2) (note 2) note 1: make sure the pd7_1 bit of pd7 register is set to 0 (= input mode). note 2: overflow or underflow (note 1) figure 1.14.6. onsf register, trgsr register, and cpsrf register
timers (timer a) 112 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. item specification count source f 1 , f 2 , f 8 , f 32 , f c32 count operation ? down-count ? when the timer underflows, it reloads the reload register contents and continues counting divide ratio 1/(n+1) n: set value of taimr register (i= 0 to 4) 0000 16 to ffff 16 count start condition set tais bit of tabsr register to 1 (= start counting) count stop condition set tais bit to 0 (= stop counting) interrupt request generation timing timer underflow tai in pin function i/o port or gate input tai out pin function i/o port or pulse output read from timer count value can be read by reading tai register write to timer ? when not counting and until the 1st count source is input after counting start value written to tai register is written to both reload register and counter ? when counting (after 1st count source input) value written to tai register is written to only reload register (transferred to counter when reloaded next) select function ? gate function counting can be started and stopped by an input signal to tai in pin ? pulse output function whenever the timer underflows, the output polarity of tai out pin is inverted. when not counting, the pin outputs a low. 1. timer mode in timer mode, the timer counts a count source generated internally (see table 1.14.1). figure 1.14.7 shows taimr register in timer mode. table 1.14.1. specifications in timer mode note 1: ta0 out pin is n-channel open drain output. note 2: the port direction bit for the tai in pin must be set to 0 (= input mode). timer ai mode register (i=0 to 4) symbol address after reset ta0mr to ta4mr 0396 16 to 039a 16 00 16 bit name functionbit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 0 : timer mode b1 b0 tmod1 tmod0 mr0 pulse output function select bit 0 : pulse is not output (ta iout pin is a normal port pin) 1 : pulse is output (note 1) (ta iout pin is a pulse output pin) gate function select bit 0 0 : gate function not available 0 1 : (tai in pin functions as i/o port) 1 0 : counts while input on the tai in pin is low (note 2) 1 1 : counts while input on the tai in pin is high (note 2) b4 b3 mr2 mr1 mr3 must be set to 0 in timer mode 0 0 : f 1 or f 2 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 tck1 tck0 count source select bit 00 0 rw rw rw rw rw rw rw rw } figure 1.14.7. timer ai mode register in timer mode
timers (timer a) 113 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. item specification count source ? external signals input to tai in pin (i=0 to 4) (effective edge can be selected in program) ? timer b2 overflows or underflows, timer aj (j=i-1, except j=4 if i=0) overflows or underflows, timer ak (k=i+1, except k=0 if i=4) overflows or underflows count operation ? up-count or down-count can be selected by external signal or program ? when the timer overflows or underflows, it reloads the reload register con- tents and continues counting. when operating in free-running mode, the timer continues counting without reloading. divided ratio 1/ (ffff 16 - n + 1) for up-count 1/ (n + 1) for down-count n : set value of tai register 0000 16 to ffff 16 count start condition set tais bit of tabsr register to 1 (= start counting) count stop condition set tais bit to 0 (= stop counting) interrupt request generation timing timer overflow or underflow tai in pin function i/o port or count source input tai out pin function i/o port, pulse output, or up/down-count select input read from timer count value can be read by reading tai register write to timer ? when not counting and until the 1st count source is input after counting start value written to tai register is written to both reload register and counter ? when counting (after 1st count source input) value written to tai register is written to only reload register (transferred to counter when reloaded next) select function ? free-run count function even when the timer overflows or underflows, the reload register content is not reloaded to it ? pulse output function whenever the timer underflows or underflows, the output polarity of tai out pin is inverted . when not counting, the pin outputs a low. 2. event counter mode in event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers. timers a2, a3 and a4 can count two-phase external signals. table 1.14.2 lists specifica- tions in event counter mode (when not processing two-phase pulse signal). table 1.14.3 lists specifica- tions in event counter mode (when processing two-phase pulse signal with the timers a2, a3 and a4). figure 1.14.8 shows taimr register in event counter mode (when not processing two-phase pulse sig- nal). figure 1.14.9 shows ta2mr to ta4mr registers in event counter mode (when processing two- phase pulse signal with the timers a2, a3 and a4). table 1.14.2. specifications in event counter mode (when not processing two-phase pulse signal)
timers (timer a) 114 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. note 1: during event counter mode, the count source can be selected using the onsf and trgsr registers. note 2: ta0 out pin is n-channel open drain output. note 3: effective when the taigh and taigl bits of onsf or trgsr register are 00 2 (tai in pin input). note 4: count down when input on tai out pin is low or count up when input on that pin is high. the port direction bit for tai out pin must be set to 0 (= input mode). symbol address a fter reset ta0mr to ta4mr 0396 16 to 039a 16 00 16 wr b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 1 : event counter mode (note 1) b1 b0 tmod0 mr0 pulse output function select bit 0 : pulse is not output (ta iout pin functions as i/o port) 1 : pulse is output (note 2) (tai out pin functions as pulse output pin) count polarity select bit (note 3) mr2 mr1 mr3 must be set to 0 in event counter mode tck0 count operation type select bit 01 0 0 : counts external signal's falling edge 1 : counts external signal's rising edge up/down switching cause select bit 0 : udf register 1 : input signal to ta iout pin (note 4) 0 : reload type 1 : free-run type bit symbol bit name function rw tck1 can be 0 or 1 when not using two-phase pulse signal processing tmod1 timer ai mode register (i=0 to 4) (when not using two-phase pulse signal processing) rw rw rw rw rw rw rw rw figure 1.14.8. taimr register in event counter mode (when not using two-phase pulse signal processing)
timers (timer a) 115 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. item specification count source ? two-phase pulse signals input to tai in or tai out pins (i = 2 to 4) count operation ? up-count or down-count can be selected by two-phase pulse signal ? when the timer overflows or underflows, it reloads the reload register con- tents and continues counting. when operating in free-running mode, the timer continues counting without reloading. divide ratio 1/ (ffff 16 - n + 1) for up-count 1/ (n + 1) for down-count n : set value of tai register 0000 16 to ffff 16 count start condition set tais bit of tabsr register to 1 (= start counting) count stop condition set tais bit to 0 (= stop counting) interrupt request generation timing timer overflow or underflow tai in pin function two-phase pulse input tai out pin function two-phase pulse input read from timer count value can be read by reading timer a2, a3 or a4 register write to timer ? when not counting and until the 1st count source is input after counting start value written to tai register is written to both reload register and counter ? when counting (after 1st count source input) value written to tai register is written to reload register (transferred to counter when reloaded next) select function (note) ? normal processing operation (timer a2 and timer a3) the timer counts up rising edges or counts down falling edges on taj in pin when input signals on taj out pin is h. ? multiply-by-4 processing operation (timer a3 and timer a4) if the phase relationship is such that tak in (k=3, 4) pin goes h when the input signal on tak out pin is h, the timer counts up rising and falling edges on tak out and tak in pins. if the phase relationship is such that tak in pin goes l when the input signal on tak out pin is h, the timer counts down rising and falling edges on tak out and tak in pins. table 1.14.3. specifications in event counter mode (when processing two-phase pulse signal with timers a2, a3 and a4) taj out up- count up- count up- count down- count down- count down- count taj in (j=2,3) tak out tak in (k=3,4) count up all edges count up all edges count down all edges count down all edges ? counter initialization by z-phase input (timer a3) the timer count value is initialized to 0 by z-phase input. notes: 1. only timer a3 is selectable. timer a2 is fixed to normal processing operation, and timer a4 is fixed to multiply-by-4 processing operation.
timers (timer a) 116 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. note 1: tck1 bit is valid for timer a3 mode register. no matter how this bit is set, timers a2 and a4 always operate in normal processing mode and x4 processing mode, respectively. note 2: if two-phase pulse signal processing is desired, following register settings are required: ? set the udf registers taip bit to 1 (two-phase pulse signal processing function enabled). ? set the trgsr registers taigh and taigl bits to 00 2 (taiin pin input). ? set the port direction bits for tai in and tai out to 0 (input mode). timer ai mode register (i=2 to 4) (when using two-phase pulse signal processing) symbol address a fter reset ta2mr to ta4mr 0398 16 to 039a 16 00 16 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 1 : event counter mode b1 b0 tmod1 tmod0 mr0 to use two-phase pulse signal processing, set this bit to 0. mr2 mr1 mr3 tck1 tck0 01 0 bit name function rw count operation type select bit two-phase pulse signal processing operation select bit (note 1)(note 2) 0 : reload type 1 : free-run type 0 : normal processing operation 1 : multiply-by-4 processing operation 001 rw rw rw rw rw rw rw rw to use two-phase pulse signal processing, set this bit to 0. to use two-phase pulse signal processing, set this bit to 1. to use two-phase pulse signal processing, set this bit to 0. figure 1.14.9. ta2mr to ta4mr registers in event counter mode (when using two-phase pulse signal processing with timer a2, a3 or a4)
timers (timer a) 117 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. mm+11 2 3 4 5 ta3 out (a phase) count source ta3 in (b phase) timer a3 int2 (z phase) (note) input equal to or greater than one clock cycle of count source note: this timing diagram is for the case where the pol bit of int2ic register = 1 (= rising edge). counter initialization by two-phase pulse signal processing this function initializes the timer count value to 0 by z-phase (counter initialization) input during two- phase pulse signal processing. this function can only be used in timer a3 event counter mode during two-phase pulse signal process- _______ ing, free-running type, x4 processing, with z-phase entered from the int2 pin. counter initialization by z-phase input is enabled by writing 0000 16 to the ta3 register and setting the tazie bit in onsf register to 1 (= z-phase input enabled). counter initialization is accomplished by detecting z-phase input edge. the active edge can be cho- sen to be the rising or falling edge by using the pol bit of int2ic register. the z-phase pulse width _______ applied to the int2 pin must be equal to or greater than one clock cycle of the timer a3 count source. the counter is initialized at the next count timing after recognizing z-phase input. figure 1.14.10 shows the relationship between the two-phase pulse (a phase and b phase) and the z phase. if timer a3 overflow or underflow coincides with the counter initialization by z-phase input, a timer a3 interrupt request is generated twice in succession. do not use the timer a3 interrupt when using this function. figure 1.14.10. two-phase pulse (a phase and b phase) and the z phase
timers (timer a) 118 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. item specification count source f 1 , f 2 , f 8 , f 32 , f c32 count operation ? down-count ? when the counter reaches 0000 16 , it stops counting after reloading a new value ? if a trigger occurs when counting, the timer reloads a new count and restarts counting divide ratio 1/n n : set value of tai register 0000 16 to ffff 16 however, the counter does not work if the divide-by-n value is set to 0000 16 . count start condition tais bit of tabsr register = 1 (start counting) and one of the following triggers occurs. ? external trigger input from the tai in pin ? timer b2 overflow or underflow, timer aj (j=i-1, except j=4 if i=0) overflow or underflow, timer ak (k=i+1, except k=0 if i=4) overflow or underflow ? the taios bit of onsf register is set to 1 (= timer starts) count stop condition ? when the counter is reloaded after reaching 0000 16 ? tais bit is set to 0 (= stop counting) interrupt request generation timing when the counter reaches 0000 16 tai in pin function i/o port or trigger input tai out pin function i/o port or pulse output read from timer an indeterminate value is read by reading tai register write to timer ? when not counting and until the 1st count source is input after counting start value written to tai register is written to both reload register and counter ? when counting (after 1st count source input) value written to tai register is written to only reload register (transferred to counter when reloaded next) select function ? pulse output function the timer outputs a low when not counting and a high when counting. table 1.14.4. specifications in one-shot timer mode 3. one-shot timer mode in one-shot timer mode, the timer is activated only once by one trigger. (see table 1.14.4.) when the trigger occurs, the timer starts up and continues operating for a given period. figure 1.14.12 shows the taimr register in one-shot timer mode.
timers (timer a) 119 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.14.12. taimr register in one-shot timer mode bit name timer ai mode register (i=0 to 4) symbol address after reset ta0mr to ta4mr 396 16 to 039a 16 00 16 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 1 0 : one-shot timer mode b1 b0 tmod1 tmod0 mr0 pulse output function select bit 0 : pulse is not output (ta iout pin functions as i/o port) 1 : pulse is output (note 1) (tai out pin functions as a pulse output pin) mr2 mr1 mr3 must be set to 0 in one-shot timer mode 0 0 : f 1 or f 2 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 tck1 tck0 count source select bit 10 0 0 : taios bit is enabled 1 : selected by taitgh to taitgl bits trigger select bit external trigger select bit (note 2) 0 : falling edge of input signal to tai in pin (note 3) 1 : rising edge of input signal to tai in pin (note 3) note 1: ta0 out pin is n-channel open drain output. note 2: effective when the taigh and taigl bits of onsf or trgsr register are 00 2 (tai in pin input). note 3: the port direction bit for the tai in pin must be set to 0 (= input mode). rw rw rw rw rw rw rw rw rw
timers (timer a) 120 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. 4. pulse width modulation (pwm) mode in pwm mode, the timer outputs pulses of a given width in succession (see table 1.14.5). the counter functions as either 16-bit pulse width modulator or 8-bit pulse width modulator. figure 1.14.13 shows taimr register in pulse width modulation mode. figures 1.14.14 and 1.14.15 show examples of how a 16-bit pulse width modulator operates and how an 8-bit pulse width modulator operates. table 1.14.5. specifications in pwm mode item specification count source f 1 , f 2 , f 8 , f 32 , f c32 count operation ? d own-count (operating as an 8-bit or a 16-bit pulse width modulator) ? the timer reloads a new value at a rising edge of pwm pulse and continues counting ? the timer is not affected by a trigger that occurs during counting 16-bit pwm ? h igh level width n / fj n : set value of tai register (i=o to 4) ? cycle time (2 16 -1) / fj fixed fj: count source frequency (f 1 , f 2 , f 8 , f 32 , f c32 ) 8-bit pwm ? high level width n x (m+1) / fj n : set value of taimr register high-order address ? cycle time (2 8 -1) x (m+1) / fj m : set value of taimr register low-order address count start condition ? external trigger input from the tai in pin ? timer b2 overflow or underflow, timer aj (j=i-1, except j=4 if i=0) overflow or underflow, timer ak (k=i+1, except k=0 if i=4) overflow or underflow ? tais bit of tabsr register is set to 1 (= start counting) count stop condition tais bit is set to 0 (= stop counting) interrupt request generation timing pwm pulse goes l tai in pin function i/o port or trigger input tai out pin function pulse output read from timer an indeterminate value is read by reading tai register write to timer ? when not counting and until the 1st count source is input after counting start value written to tai register is written to both reload register and counter ? when counting (after 1st count source input) value written to tai register is written to only reload register (transferred to counter when reloaded next)
timers (timer a) 121 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.14.13. taimr register in pwm mode bit name timer ai mode register (i= 0 to 4) symbol address a fter reset ta0mr to ta4mr 0396 16 to 039a 16 00 16 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 1 1 : pwm mode b1 b0 tmod1 tmod0 mr0 mr2 mr1 mr3 0 0 : f 1 or f 2 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 tck1 tck0 count source select bit rw 11 1 must be set to 1 in pwm mode 16/8-bit pwm mode select bit 0: functions as a 16-bit pulse width modulator 1: functions as an 8-bit pulse width modulator trigger select bit external trigger select bit (note 2) 0: falling edge of input signal to tai in pin(note 3) 1: rising edge of input signal to tai in pin(note 3) rw rw rw rw rw rw rw rw (note 1) 0 : taios bit is enabled 1 : selected by taitgh to taitgl bits note 1: ta0 out pin is n-channel open drain output. note 2: effective when the taigh and taigl bits of onsf or trgsr register are 00 2 (tai in pin input). note 3: the p ort direction bit for the tai in p in must be set to 0 ( = in p ut mode ) .
timers (timer a) 122 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. 1 / f i x (2 C 1) 16 count source input signal to ta iin pin pwm pulse output from ta iout pin trigger is not generated by this signal h h l l ir bit of taiic register 1 0 f j : frequency of count source (f 1 , f 2 , f 8 , f 32 , f c32 ) i = 0 to 4 note 1: n = 0000 16 to fffe 16 . note 2: this timing diagram is for the case where the tai register is 0003 16 , the taigh and taigl bits of onsf or trgsr register = 00 2 (tai in pin input), the mr1 bit of taimr register = 1 (rising edge), and the mr2 bit of taimr register = 1 (trigger selected by taitgh and taitgl bits). 1 / f j x n set to 0 upon accepting an interrupt request or by writing in program count source (note1) input signal to ta iin pin underflow signal of 8-bit prescaler (note2) pwm pulse output from ta iout pin h h h l l l 1 0 set to 0 upon accepting an interrupt request or by writing in program note 1: the 8-bit prescaler counts the count source. note 2: the 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal. note 3: m = 00 16 to ff 16 ; n = 00 16 to fe 16 . note 4: this timing diagram is for the case where the tai register is 0202 16 , the taigh and taigl bits of onsf or trgsr register = 00 2 (tai in pin input), the mr1 bit of taimr register = 0 (falling edge), and the mr2 bit of taimr register = 1 (trigger selected by taitgh and taitgl bits). aaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaa 1 / f j x (m + 1) x (2 e 1) 8 1 / f j x (m + 1) x n 1 / f j x (m + 1) ir bit of taiic register f j : frequency of count source (f 1 , f 2 , f 8 , f 32 , f c32 ) i = 0 to 4 figure 1.14.14. example of 16-bit pulse width modulator operation figure 1.14.15. example of 8-bit pulse width modulator operation
timers (timer b) 123 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. timer b figure 1.15.1 shows a block diagram of the timer b. figures 1.15.2 and 1.15.3 show registers related to the timer b. timer b supports the following three modes. use the tmod1 and tmod0 bits of tbimr register (i = 0 to 5) to select the desired mode. ? timer mode: the timer counts an internal count source. ? event counter mode: the timer counts pulses from an external device or overflows or underflows of other timers. ? pulse period/pulse width measuring mode: the timer measures an external signal's pulse period or pulse width. figure 1.15.1. timer b block diagram timer bi mode register (i=0 to 5) symbol address after reset tb0mr to tb2mr 039b 16 to 039d 16 00xx0000 2 tb3mr to tb5mr 035b 16 to 035d 16 00xx0000 2 bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 0 0 : timer mode 0 1 : event counter mode 1 0 : pulse period measurement mode, pulse width measurement mode 1 1 : must not be set b1 b0 tck1 mr3 mr2 mr1 tmod1 mr0 tmod0 tck0 function varies with each operation mode count source select bit operation mode select bit (note 1) (note 2) note 1: timer b0, timer b3. note 2: timer b1, timer b2, timer b4, timer b5. rw rw rw rw rw rw rw ro function varies with each operation mode clock source selection ? event counter ? timer ? pulse period measuremnet, pulse width measurement reload register low-order 8 bits high-order 8 bits data bus low-order bits data bus high-order bits f 1 or f 2 f 8 f 32 tbj overflow (note) (j = i C 1. note, however, j = 2 when i = 0, j = 5 when i = 3) can be selected in only event counter mode tabsr register tbsr register f c32 polarity switching and edge pulse tbi in (i = 0 to 5) counter reset circuit counter tbi address tbj timer b0 0391 16 0390 16 timer b2 timer b1 0393 16 0392 16 timer b0 timer b2 0395 16 0394 16 timer b1 timer b3 0351 16 0350 16 timer b5 timer b4 0353 16 0352 16 timer b3 timer b5 0355 16 0354 16 timer b4 clock selection note: overflow or underflow. figure 1.15.2. tb0mr to tb5mr registers
timers (timer b) 124 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. symbol address a fter reset tabsr 0380 16 00 16 count start flag bit name bit symbol b7 b6 b5 b4 b3 b2 b1 b0 aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa timer b2 count start flag timer b1 count start flag timer b0 count start flag timer a4 count start flag timer a3 count start flag timer a2 count start flag timer a1 count start flag timer a0 count start flag 0 : stops counting 1 : starts counting tb2s tb1s tb0s ta4s ta3s ta2s ta1s ta0s function symbol address a fter reset cpsrf 0 381 16 0xxxxxxx 2 clock prescaler reset flag bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa clock prescaler reset flag cpsr symbol address a fter reset tb0 0391 16 , 0390 16 indeterminate tb1 0393 16 , 0392 16 indeterminate tb2 0395 16 , 0394 16 indeterminate tb3 0351 16 , 0350 16 indeterminate tb4 0353 16 , 0352 16 indeterminate tb5 0355 16 , 0354 16 indeterminate b7 b0 b7 b0 (b15) (b8) timer bi register (i=0 to 5)(note 1) rw measures a pulse period or width function symbol address a fter reset tbsr 0340 16 000xxxxx 2 timer b3, b4, b5 count start flag bit name bit symbol b7 b6 b5 b4 b3 b2 b1 b0 aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa timer b5 count start flag timer b4 count start flag timer b3 count start flag 0 : stops counting 1 : starts counting tb5s tb4s tb3s nothing is assigned. when write, set to 0. when read, their contents are indeterminate. function nothing is assigned. when write, set to 0. when read, their contents are indeterminate. rw rw ro rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw (b4-b0) (b6-b0) note 1: the register must be accessed in 16 bit units. note 2: the timer counts pulses from an external device or overflows or underflows of other timers. divide the count source by n + 1 where n = set value timer mode event counter mode 0000 16 to ffff 16 divide the count source by n + 1 where n = set value (note 2) 0000 16 to ffff 16 pulse period modulation mode, pulse width modulation mode setting this bit to 1 initializes the prescaler for the timekeeping clock. (when read, the value of this bit is 0.) mode setting range figure 1.15.3. tb0 to tb5 registers, tabsr register, tbsr register, cpsrf register
timers (timer b) 125 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. item specification count source f 1 , f 2 , f 8 , f 32 , f c32 count operation ? down-count ? when the timer underflows, it reloads the reload register contents and continues counting divide ratio 1/(n+1) n: set value of tbimr register (i= 0 to 5) 0000 16 to ffff 16 count start condition set tbis bit (note) to 1 (= start counting) count stop condition set tbis bit to 0 (= stop counting) interrupt request generation timing timer underflow tbi in pin function i/o port read from timer count value can be read by reading tbi register write to timer ? when not counting and until the 1st count source is input after counting start value written to tbi register is written to both reload register and counter ? when counting (after 1st count source input) value written to tbi register is written to only reload register (transferred to counter when reloaded next) note : the tb0s to tb2s bits are assigned to the tabsr register bit 5 to bit 7, and the tb3s to tb5s bits are assigned to the tbsr register bit 5 to bit 7. 1. timer mode in timer mode, the timer counts a count source generated internally (see table 1.15.1). figure 1.15.4 shows tbimr register in timer mode. table 1.15.1. specifications in timer mode timer bi mode register (i= 0 to 5) symbol address a fter reset tb0mr to tb2mr 039b 16 to 039d 16 00xx0000 2 tb3mr to tb5mr 035b 16 to 035d 16 00xx0000 2 bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 aa aa a a operation mode select bit 0 0 : timer mode b1 b0 tmod1 tmod0 mr0 has no effect in timer mode can be set to 0 or 1 mr2 mr1 mr3 0 0 : f 1 or f 2 0 1 : f 8 1 0 : f 32 1 1 : f c32 tck1 tck0 count source select bit 0 0 tb0mr, tb3mr registers must be set to 0 in timer mode b7 b6 rw rw rw rw rw rw rw ro tb1mr, tb2mr, tb4mr, tb5mr registers nothing is assigned. when write, set to 0. when read, its content is indeterminate when write in timer mode, set to 0. when read in timer mode, its content is indeterminate. figure 1.15.4. tbimr register in timer mode
timers (timer b) 126 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. item specification count source ? external signals input to tbi in pin (i=0 to 5) (effective edge can be selected in program) ? timer bj overflow or underflow (j=i-1, except j=2 if i=0, j=5 if i=3) count operation ? down-count ? when the timer underflows, it reloads the reload register contents and continues counting divide ratio 1/(n+1) n: set value of tbi register 0000 16 to ffff 16 count start condition set tbis bit 1 to 1 (= start counting) count stop condition set tbis bit to 0 (= stop counting) interrupt request generation timing timer underflow tbi in pin function count source input read from timer count value can be read by reading tbi register write to timer ? when not counting and until the 1st count source is input after counting start value written to tbi register is written to both reload register and counter ? when counting (after 1st count source input) value written to tbi register is written to only reload register (transferred to counter when reloaded next) notes: 1. the tb0s to tb2s bits are assigned to the tabsr register bit 5 to bit 7, and the tb3s to tb5s bits are assigned to the tbsr register bit 5 to bit 7. 2. event counter mode in event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers (see table 1.15.2) . figure 1.15.5 shows tbimr register in event counter mode. table 1.15.2. specifications in event counter mode figure 1.15.5. tbimr register in event counter mode timer bi mode register (i=0 to 5) symbol address after reset tb0mr to tb2mr 039b 16 to 039d 16 00xx0000 2 tb3mr to tb5mr 035b 16 to 035d 16 00xx0000 2 bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 aa operation mode select bit 0 1 : event counter mode b1 b0 tmod1 tmod0 mr0 count polarity select bit (note 1) mr2 mr1 mr3 tck1 tck0 01 0 0 : counts external signal's falling edges 0 1 : counts external signal's rising edges 1 0 : counts external signal's falling and rising edges 1 1 : must not be set b3 b2 note 1: effective when the tck1 bit = 0 (input from tbiin pin). if the tck1 bit = 1 (tbj overflow or underflow), these bits can be set to 0 or 1. note 2: the port direction bit for the tbi in pin must be set to 0 (= input mode). has no effect in event counter mode. can be set to 0 or 1. event clock select 0 : input from tbi in pin (note 2) 1 : tbj overflow or underflow (j = i e 1, except j = 2 if i = 0, j = 5 if i = 3) rw rw rw rw rw rw rw ro tb0mr, tb3mr registers must be set to 0 in timer mode tb1mr, tb2mr, tb4mr, tb5mr registers nothing is assigned. when write, set to 0. when read, its content is indeterminate. when write in event counter mode, set to 0. when read in event counter mode, its content is indeterminate.
timers (timer b) 127 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. item specification count source f 1 , f 2 , f 8 , f 32 , f c32 count operation ? up-count ? counter value is transferred to reload register at an effective edge of mea- surement pulse. the counter value is set to 0000 16 to continue counting. count start condition set tbis (i=0 to 5) bit 3 to 1 (= start counting) count stop condition set tbis bit to 0 (= stop counting) interrupt request generation timing ? when an effective edge of measurement pulse is input 1 ? timer overflow. when an overflow occurs, mr3 bit of tbimr register is set to 1 (overflowed) simultaneously. mr3 bit is cleared to 0 (no overflow) by writing to tbimr register at the next count timing or later after mr3 bit was set to 1. at this time, make sure tbis bit is set to 1 (start counting). tbi in pin function measurement pulse input read from timer contents of the reload register (measurement result) can be read by reading tbi register 2 write to timer value written to tbi register is written to neither reload register nor counter notes: 1. interrupt request is not generated when the first effective edge is input after the timer started counting. 2. value read from tbi register is indeterminate until the second valid edge is input after the timer starts counting. 3. the tb0s to tb2s bits are assigned to the tabsr register bit 5 to bit 7, and the tb3s to tb5s bits are assigned to the tbsr register bit 5 to bit 7. 3. pulse period and pulse width measurement mode in pulse period and pulse width measurement mode, the timer measures pulse period or pulse width of an external signal (see table 1.15.3). figure 1.15.6 shows tbimr register in pulse period and pulse width measurement mode. figure 1.15.7 shows the operation timing when measuring a pulse period. figure 1.15.8 shows the operation timing when measuring a pulse width. table 1.15.3. specifications in pulse period and pulse width measurement mode figure 1.15.6. tbimr register in pulse period and pulse width measurement mode timer bi mode register (i=0 to 5) symbol address after reset tb0mr to tb2mr 039b 16 to 039d 16 00xx0000 2 tb3mr to tb5mr 035b 16 to 035d 16 00xx0000 2 bit name bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 1 0 : pulse period / pulse width measurement mode b1 b0 tmod1 tmod0 mr0 measurement mode select bit mr2 mr1 mr3 tck1 tck0 01 0 0 : pulse period measurement (measurement between a falling edge and the next falling edge of measured pulse) 0 1 : pulse period measurement (measurement between a rising edge and the next rising edge of measured pulse) 1 0 : pulse width measurement (measurement between a falling edge and the next rising edge of measured pulse and between a rising edge and the next falling edge) 1 1 : must not be set. function b3 b2 count source select bit timer bi overflow flag ( note) 0 : timer did not overflow 1 : timer has overflowed 0 0 : f 1 or f 2 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 note: this flag is indeterminate after reset. when the tbis bit = 1 (start counting), the mr3 bit is cleared to 0 (no overflo w) by writing to the tbimr register at the next count timing or later after the mr3 bit was set to 1 (overflowed). the mr3 bit cannot be se t to 1 in a program. the tb0s to tb2s bits are assigned to the tabsr register's bit 5 to bit 7, and the tb3s to tb5s bits are assigned to the tbsr register's bit 5 to bit 7. rw rw rw rw rw rw rw ro tb0mr and tb3mr registers must be set to 0 in pulse period and pulse width measurement mode tb1mr, tb2mr, tb4mr, tb5mr registers nothing is assigned. when write, set to 0. when read, its content turns out to be indeterminate.
timers (timer b) 128 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.15.8. operation timing when measuring a pulse width measurement pulse h count source timing at which counter reaches 0000 16 1 1 transfer (measured value) transfer (measured value) l 0 0 1 0 (note 1) (note 1)(note 1) transfer (measured value) (note 1) (note 2) transfer (indeterminate value) reload register counter transfer timing tbis bit tbiic register's ir bit tbimr register's mr3 bit note 1: counter is initialized at completion of measurement. note 2: timer has overflowed. note 3: this timing diagram is for the case where the tbimr register's mr1 to mr0 bits are 10 2 (measure the interval from a falling edge to the next rising edge and the interval from a rising edge to the next falling edge of the measurement pulse). the tb0s to tb2s bits are assigned to the tabsr register's bit 5 to bit 7, and the tb3s to tb5s bits are assigned to the tbsr register's bit 5 to bit 7. set to 0 upon accepting an interrupt request or by writing in program i = 0 to 5 figure 1.15.7. operation timing when measuring a pulse period count source measurement pulse tbis bit tbiic register's ir bit timing at which counter reaches 0000 16 h 1 transfer (indeterminate value) l 0 0 tbimr register's mr3 bit 1 0 note 1: counter is initialized at completion of measurement. note 2: timer has overflowed. note 3: this timing diagram is for the case where the tbimr register's mr1 to mr0 bits are 00 2 (measure the interval from falling edge to falling edge of the measurement pulse). (note 1)(note 1) (note 2) transfer (measured value) 1 reload register counter transfer timing the tb0s to tb2s bits are assigned to the tabsr register's bit 5 to bit 7, and the tb3s to tb5s bits are assigned to the tbsr register's bit 5 to bit 7. set to 0 upon accepting an interrupt request or by writing in program i = 0 to 5
three-phase motor control timer functions 129 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. three-phase motor control timer function timers a1, a2, a4 and b2 can be used to output three-phase motor drive waveforms. table 1.16.1 lists the specifications of the three-phase motor control timer function. figure 1.16.1 shows the block diagram for three-phase motor control timer function. also, the related registers are shown on figure 1.16.2 to figure 1.16.7. table 1.16.1. three-phase motor control timer functions specifications item specification three-phase waveform output pin ___ ___ ___ six pins (u, u, v, v, w, w) forced cutoff input 1 _______ input l to nmi pin used timers timer a4, a1, a2 (used in the one-shot timer mode) ___ timer a4: u- and u-phase waveform control ___ timer a1: v- and v-phase waveform control ___ timer a2: w- and w-phase waveform control timer b2 (used in the timer mode) carrier wave cycle control dead timer timer (3 eight-bit timer and shared reload register) dead time control output waveform triangular wave modulation, sawtooth wave modification enable to output h or l for one cycle enable to set positive-phase level and negative-phase level respectively carrier wave cycle triangular wave modulation: count source x (m+1) x 2 sawtooth wave modulation: count source x (m+1) m: setting value of tb2 register, 0 to 65535 count source: f 1 , f 2 , f 8 , f 32 , f c32 three-phase pwm output width triangular wave modulation: count source x n x 2 sawtooth wave modulation: count source x n n: setting value of ta4, ta1 and ta2 register (of ta4, ta41, ta1, ta11, ta2 and ta21 registers when setting the inv11 bit to 1), 1 to 65535 count source: f 1 , f 2 , f 8 , f 32 , f c32 dead time count source x p, or no dead time p: setting value of dtt register, 1 to 255 count source: f 1 , f 2 , f 1 divided by 2, f 2 divided by 2 active level eable to select h or l positive and negative-phase concurrent positive and negative-phases concurrent active disable function positive and negative-phases concurrent active detect func tion interrupt frequency for timer b2 interrupt, select a carrier wave cycle-to-cycle basis through 15 times carrier wave cycle-to-cycle basis active disable function notes: _______ 1. forced cutoff with nmi input is effective when the ivpcr1 bit of tb2sc register is set to 1 (three-phase _______ _______ output forcible cutoff by nmi input enabled). if an l signal is applied to the nmi pin when the ivpcr1 bit is 1, the related pins go to a high-impedance state regardless of which functions of those pins are being used. related pins p7 2 /clk 2 /ta1 out /v _________ _________ ___ p7 3 /cts 2 /rts 2 /ta1 in /v p7 4 /ta2 out /w ____ p7 5 /ta2 in /w p8 0 /ta4 out /u ___ p8 1 /ta4 in /u
three-phase motor control timer functions 130 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. d r q 0 in v12 1 t rigger t rigger ti m er b2 (t im er m ode) signal to be w ritten to tim er b2 1 ti m er b2 interrupt request bit du 1 bit d t q q q u three-phase output shift register (u phase) dead tim e tim er n = 1 to 255 t rigger t rigger r eload register n = 1 to 255 t rigger t rigger u phase output signal u v v v w w w phase output control circuit d q t d q t w d q t d q t v d q t u d q t r everse control u w v r eload ti m er a 1 counter (o ne-shot tim er m ode) t rigger tq reload ti m er a 2 counter (o ne-shot tim er m ode) t rigger tq reload ti m er a4 counter (o ne-shot tim er m ode) t rigger tq t ransfer trigger (n ote 1) ti m er b2 underflow d u 0 bit d ub0 bit t a4 register t a41 register ta 1 register ta 11 register ta 2 register t a21 register t imer ai(i = 1, 2, 4) start trigger signal t imer a4 reload control signal t imer a4 one-shot pulse d u b1 bit dead tim e tim er n = 1 to 255 dead tim e tim er n = 1 to 255 interrupt occurrence set circuit ictb2 register n = 1 to 15 0 inv13 ictb2 counter n = 1 to 15 reset nmi inv03 inv14 inv05 inv04 inv00 inv01 inv1 1 inv1 1 inv1 1 inv1 1 inv06 inv06 inv06 inv07 inv10 1/2 f1 phase output control circuit phase output control circuit phase output signal phase output signal phase output signal phase output signal phase output signal reverse control reverse control reverse control r everse control r everse control d t d t q d t note : if the inv06 bit = 0 (triangular wave modulation mode), a transfer trigger is generated at only the first occurrence of a timer b2 underflow after writing to the idb0 and idb1 registers. set to 0 when t a2s bit = 0 set to 0 when t a1s bit = 0 set to 0 when t a4s bit = 0 diagram for switching to p8 0 , p81 and p7 2 - p7 5 is not shown. figure 1.16.1. three-phase motor control timer functions block diagram
three-phase motor control timer functions 131 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. three-phase pwm control register 0 (note 1) symbol address a fter reset invc0 0348 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 effective interrupt output polarity select bit inv00 bit symbol bit name description rw inv01 effective interrupt output specification bit inv02 mode select bit inv04 positive and negative phases concurrent output disable function enable bit inv07 s oftware trigger select bit inv06 modulation mode select bit inv05 positive and negative phases concurrent output detect flag inv03 output control bit 0: ictb2 counter incremented by 1 at odd-numbered occurrences of a timer b2 underflow 1: ictb2 counter incremented by 1 at even-numbered occurrences of a timer b2 underflow 0: ictb2 counter incremented by 1 at a timer b2 underflow 1: selected by inv00 bit 0: three-phase motor control timer function unused 1: three-phase motor control timer function 0: three-phase motor control timer output disabled 1: three-phase motor control timer output enabled 0: simultaneous active output enabled 1: simultaneous active output disabled 0: not detected yet 1: already detected 0: triangular wave modulation mode 1: sawtooth wave modulation mode setting this bit to 1 generates a transfer trigger. if the inv06 bit is 1, a trigger for the dead time timer is also generated. the value of this bit when read is 0. (note 9) (note 3) (note 3) (note 7) (note 2) note 1: write to this register after setting the prc1 bit of prcr register to 1 (write enable). note also that this register can only be rewritten when timers a1, a2, a4 and b2 are idle. note 2: if this bit needs to be set to 1, set any value in the ictb2 register before writing to it. note 3: effective when the inv11 bit is 1 (three-phase mode 1). if inv11 is 0 (three-phase mode 0), the ictb2 counter is incremented by 1 each time the timer b2 underflows, regardless of whether the inv00 and inv01 bits are set. note 4: setting the inv02 bit to 1 activates the dead time timer, u/v/w-phase output control circuits and ictb2 counter. note 5: all of the u, u, v, v, w and w pins are placed in the high-impedance state by setting the inv02 bit to 1 (three- phase motor control timer function) and setting the inv03 bit to 0 (three-phase motor control timer output disable). note 6: the inv03 bit is set to 0 in the following cases: ? when reset ? when positive and negative go active simultaneously while inv04 bit is 1 ? when set to 0 in a program ? when input on the nmi pin changes state from h to l (the inv03 bit cannot be set to 1 when nmi input is l.) note 7: can only be set by writing 0 in a program, and cannot be set to 1. note 8: the effects of the inv06 bit are described in the table below. (note 4) rw rw rw rw rw rw rw rw (note 5) (note 8) item mode timing at which transferred from idb0 to idb1 registers to three-phase output shift register timing at which dead time timer trigger is generated when inv16 bit is 0 inv13 bit inv06=0 triangular wave modulation mode transferred only once synchronously with the transfer trigger after writing to the idb0 to idb1 registers synchronous with the falling edge of timer a1, a2, or a4 one-shot pulse effective when inv11 is 1 and inv06 is 0 inv06=1 sawtooth wave modulation mode transferred every transfer trigger synchronous with the transfer trigger and the falling edge of timer a1, a2, or a4 one-shot pulse transfer trigger: timer b2 underflow, write to the inv07 bit or write to the tb2 register when inv10 is 1 note 9: if the inv06 bit is 1, set the inv11 bit to 0 (three-phase mode 0) and set the pwcon bit to 0 (timer b2 reloaded by a timer b2 underflow). (note 6) (note 5) has no effect figure 1.16.2. invc0 register
three-phase motor control timer functions 132 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.16.3. invc1 register three-phase pwm control register 1 (note 1) symbol a ddress after reset invc1 0349 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 timer a1, a2, a4 start trigger signal select bit inv10 bit symbol bit name description rw inv11 timer a1-1, a2-1, a4-1 control bit inv12 dead time timer count source select bit inv14 output polarity control bit (b7) reserved bit inv16 dead time timer trigger select bit inv15 dead time invalid bit inv13 carrier wave detect flag 0: timer b2 underflow 1: timer b2 underflow and write to the tb2 register 0: three-phase mode 0 1: three-phase mode 1 0 : f 1 or f 2 1 : f 1 divided by 2 or f 2 divided by 2 0: timer a output at even-numbered occ- urrences (taj1 register value counted) 1: timer a output at odd-numbered occ- urrences (taj1 register value counted) 0 : output waveform l active 1 : output waveform h active 0: dead time timer enabled 1: dead time timer disabled 0: falling edge of timer a4, a1 or a2 one-shot pulse 1: rising edge of three-phase output shift register (u, v or w phase) output this bit should be set to 0 note 1: write to this register after setting the prc1 bit of prcr register to 1 (write enable). note also that this register can only be rewritten when timers a1, a2, a4 and b2 are idle. note 2: the effects of the inv11 bit are described in the table below. (note 5) (note 4) rw rw rw rw rw rw rw ro (note 2) item mode ta11, ta21, ta41 registers inv00 bit, inv01 bit inv13 bit inv11=0 three-phase mode 1 three-phase mode 0 not used has no effect. ictb2 counted every time timer b2 underflows regardless of whether the inv00 to inv01 bits are set. has no effect inv11=1 used effect effective when inv11 bit is 1 and inv06 bit is 0 note 3: if the inv06 bit is 1 (sawtooth wave modulation mode), set this bit to 0 (three-phase mode 0). also, if the inv11 bit is 0, set the pwcon bit to 0 (timer b2 reloaded by a timer b2 underflow). note 4: the inv13 bit is effective only when the inv06 bit is 0 (triangular wave modulation mode) and the inv11 bit is 1 (three-phase mode 1). note 5: if all of the following conditions hold true, set the inv16 bit to 1 (dead time timer triggered by the rising edge of three-phase output shift register output) ? the inv15 bit is 0 (dead time timer enabled) ? when the inv03 bit is set to 1 (three-phase motor control timer output enabled), the dij bit and dibj bit (i:u, v, or w, j: 0 to 1) have always different values (the positive-phase and negative-phase always output different levels during the period other than dead time). conversely, if either one of the above conditions holds false, set the inv16 bit to 0 (dead time timer triggered by the falling edge of one-shot pulse). (note 3)
three-phase motor control timer functions 133 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. three-phase output buffer register i (i=0, 1) (note) symbol address a fter reset idb0 034a 16 00 16 idb1 034b 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 dui dubi dvi dwi dvbi dwbi u phase output buffer i write the output level 0: active level 1: inactive level when read, these bits show the three-phase output shift register value. v phase output buffer i w phase output buffer i u phase output buffer i v phase output buffer i w phase output buffer i dead time timer (note 1, note 2) symbol address a fter reset dtt 034c 16 indeterminate function setting range b7 b0 assuming the set value = n, upon a start trigger the timer starts counting the count source selected by the inv12 bit and stops after counting it n times. the positive or negative phase whichever is going from an inactive to an active level changes at the same time the dead time timer stops. 1 to 255 note: the idb0 and idb1 register values are transferred to the three-phase shift register by a transfer trigger. the value written to the idb0 register after a transfer trigger represents the output signal of each phase, and the next value written to the idb1 register at the falling edge of the timer a1, a2 or a4 one-shot pulse represents the output signal of each phase. note 1: use mov instruction to write to this register. note 2: effective when the inv15 bit is 0 (dead time timer enable). if the inv15 bit is 1, the dead time timer is disabled and has no effect. rw rw rw rw rw rw rw nothing is assigned. when write, set to 0. when read, its content is 0. (b7-b6) rw wo figure 1.16.4. idb0 register, idb1register, and dtt register
three-phase motor control timer functions 134 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. symbol address a fter reset ta1 0389 16 -0388 16 indeterminate ta2 038b 16 -038a 16 indeterminate ta4 038f 16 -038e 16 indeterminate ta11 0343 16 -0342 16 indeterminate ta21 0345 16 -0344 16 indeterminate ta41 0347 16 -0346 16 indeterminate b7 b0 b7 b0 (b15) (b8) rw assuming the set value = n, upon a start trigger the timer starts counting the count source and stops after counting it n times. the positive and negative phases change at the same time timer a, a2 or a4 stops. function setting range timer ai, ai-1 register (i=1, 2, 4) (note 1, note 2, note 3, note 4, note 5, note 6) note 1: the register must be accessed in 16 bit units. note 2: when the timer ai register is set to 0000 16 , the counter does not operate and a timer ai interrupt does not occur. note 3: use mov instruction to write to these registers. note 4: if the inv15 bit is 0 (dead time timer enable), the positive or negative phase whichever is going from an inactive to an active level changes at the same time the dead time timer stops. note 5: if the inv11 bit is 0 (three-phase mode 0), the tai register value is transferred to the reload register by a timer ai (i = 1, 2 or 4) start trigger. if the inv11 bit is 1 (three-phase mode 1), the tai1 register value is transferred to the reload register by a timer ai start trigger first and then the tai register value is transferred to the reload register by the next timer ai start trigger. thereafter, the tai1 register and tai register values are transferred to the reload register alternately. note 6: do not write to these registers synchronously with a timer b2 underflow. note 7: write to the tai1 register as follows: (1) write a value to the tai1 register. (2) wait for one cycle of timer ai count source. (3) write the same value to the tai1 register again. wo 0000 16 to ffff 16 pwcom symbol address after reset tb2sc 039e 16 xxxxxx00 2 timer b2 reload timing switching bit 0 : timer b2 underflow 1 : timer a output at odd-numbered occurrences timer b2 special mode register bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 nothing is assigned. when write, set to 0. when read, its content is 0. ivpcr1 three phase output port nmi control bit 1 0 : three-phase output forcible cutoff by nmi input (high impedance) disabled 1 : three-phase output forcible cutoff by nmi input (high impedance) enabled (note 3) note 1: write to this register after setting the prc1 bit of prcr register to 1 (write enable). note 2: if the inv11 bit is 0 (three-phase mode 0) or the inv06 bit is 1 (triangular wave modulation mode), set this bit to 0 (timer b2 underflow). note 3: related pins are u(p8 0 ), u(p8 1 ), v(p7 2 ), v(p7 3 ), w(p7 4 ) and w(p7 5 ). if a low-level signal is applied to the nmi pin when the ivpcr1 bit = 1, the target pins go to a high-impedance state regardless of which functions of those pins are being used. after forced interrupt (cutoff), input h to the nmi pin and set ivpcr1 bit to 0: this forced cutoff will be reset. rw rw rw (b7-b2) (note 2) figure 1.16.5. ictb2 register, ta1, ta2, ta4, ta11, ta21 and ta41 registers, and tb2sc registers timer b2 interrupt occurrences frequency set counter symbol address after reset ictb2 034d 16 indeterminate function setting range b3 b0 if the inv01 bit is 0 (ictb2 counter counted every time timer b2 underflows), assuming the set value = n, a timer b2 interrupt is generated at every nth occurrence of a timer b2 underflow. if the inv01 bit is 1 (ictb2 counter count timing selected by the inv00 bit), assuming the set value = n, a timer b2 interrupt is generated at every nth occurrence of a timer b2 underflow that meets the condition selected by the inv00 bit. 1 to 15 note : use mov instruction to write to this register. if the inv01 bit = 1, make sure the tb2s bit also = 0 (timer b2 count stopped) when writing to this register. if the inv01 bit = 0, although this register can be written even when the tb2s bit = 1 (timer b2 count start), do not write synchronously with a timer b2 underflow. rw wo (note) nothing is assigned. when write, set to 0. when read, its content is indeterminate.
three-phase motor control timer functions 135 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.16.6. tb2 register, trgsr register, and tabsr register ta1tgl symbol address a fter reset trgsr 0383 16 00 16 timer a1 event/trigger select bit to use the v-phase output control circuit, set these bits to 01 2 (tb2 underflow). trigger select register bit name function bit symbol b0 to use the w-phase output control circuit, set these bits to 01 2 (tb2 underflow). 0 0 : input on ta3 in is selected (note 1) 0 1 : tb2 overflow is selected (note 2) 1 0 : ta2 overflow is selected (note 2) 1 1 : ta4 overflow is selected (note 2) to use the u-phase output control circuit, set these bits to 01 2 (tb2 underflow). timer a2 event/trigger select bit timer a3 event/trigger select bit timer a4 event/trigger select bit rw ta1tgh ta2tgl ta2tgh ta3tgl ta3tgh ta4tgl ta4tgh b5 b4 note 1: set the corresponding port direction bit to 0 (input mode). note 2: overflow or underflow. b7 b6 b5 b4 b3 b2 b1 symbol address after reset tabsr 0380 16 00 16 count start flag bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa timer b2 count start flag timer b1 count start flag timer b0 count start flag timer a4 count start flag timer a3 count start flag timer a2 count start flag timer a1 count start flag timer a0 count start flag 0 : stops counting 1 : starts counting tb2s tb1s tb0s ta4s ta3s ta2s ta1s ta0s rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw symbol address a fter reset tb2 0395 16 -0394 16 indeterminate b7 b0 b7 b0 (b15) (b8) rw 0000 16 to ffff 16 function setting range timer b2 register (note ) note : the register must be accessed in 16 bit units. rw divide the count source by n + 1 where n = set value. timer a1, a2 and a4 are started at every occurrence of underflow.
three-phase motor control timer functions 136 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. bit name timer ai mode register symbol address a fter reset ta1mr 0397 16 00 16 ta2mr 0 398 16 00 16 ta4mr 0 39a 16 00 16 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit must set to 10 2 (one-shot timer mode) for the three-phase motor control timer function tmod1 tmod0 mr0 pulse output function select bit must set to 0 for the three-phase motor control timer function mr2 mr1 mr3 must set to 0 for the three-phase motor control timer function 0 0 : f 1 or f 2 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 tck1 tck0 count source select bit 10 0 must set to 1 (selected by event/trigger select register) for the three-phase motor control timer function trigger select bit external trigger select bit rw timer b2 mode register symbol address a fter reset tb2mr 039d 16 00xx0000 2 bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 a a aa aa operation mode select bit set to 00 2 (timer mode) for the three- phase motor control timer function tmod1 tmod0 mr0 mr2 mr1 mr3 0 0 : f 1 or f 2 0 1 : f 8 1 0 : f 32 1 1 : f c32 tck1 tck0 count source select bit 0 when write in three-phase motor control timer function, write 0. when read, its content is indeterminate. 0 b7 b6 1 0 has no effect for the three-phase motor control timer function rw rw rw rw rw rw rw rw rw rw rw rw rw rw ro has no effect for the three-phase motor control timer function. when write, set to 0. when read, its content is indeterminate. must set to 0 for the three-phase motor control timer function figure 1.16.7. ta1mr, ta2mr, ta4mr, and tb2mr registers
three-phase motor control timer functions 137 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. start trigger signal for timer a4* timer b2 u phase c arr i er wave signal wave u phase output signal * m nn p p m u phase u phase u phase inv14 = 0 timer a4 one-shot pulse* inv14 = 1 dead time dead time transfer to three-phase output shift register rewriting idb0, idb1 registers * internal signals. see the block diagram of the three-phase motor control timer function. an example for changing pwm outputs is shown below. (1)when inv11=1(three-phase mode 1) inv01=0, ictb2=2 16 (timer b2 interrupt is generated at every 2th occurrence of a timer b2 underflow), or inv01=1, inv00=1, ictb2=1 16 (timer b2 interrupt is generated at even-numbered occurrences of a timer b2 underflow). initial timer value: ta41=m, ta4=m. the ta4 and ta41 registers are modified every time a timer b2 interrupt occurs. first time, ta41= n, ta4 = n. second time, ta41 = p, ta4 = p. initial values of idb0 and idb1 registers: du0 = 1, dub0 = 0, du1 = 0, dub1 = 1.the register values are changed to du0 = 1, dub0 = 0, du1= 1 and dub1 = 0 the third time a timer b2 interrupt occurs. (2)when inv11=0(three-phase mode 0) inv01=0, ictb2=1 16 (timer b2 interrupt is generated at every occurrence of a timer b2 underflow) initial timer value: ta4 = m. the ta4 register is modified each time a timer b2 interrupt occurs. first time, ta4 = m. second time, ta4 = n. third time, ta4 = n. fourth time, ta4 = p. fifth time, ta4 = p. initial values of idb0 and idb1 registers: du0=1, dub0=0, du1=0, dub1=1.the register values are changed to du0 = 1, dub0 = 0, du1= 1 and dub1 = 0 the sixth time a timer b2 interrupt occurs. tb2s bit of the tabsr register inv13 (inv11=1(three-phase mode 1)) shown here is a typical waveform for the case where invc0 = 00xx11xx 2 (x = set as suitable for the system) and invc1 = 010xxxx0 2 . u phase output signal * (l active) (h active) the value written to the ta4 register and ta41 register are inverted at odd-numbered timer a outputs. figure 1.16.8. triangular wave modulation operation the three-phase motor control timer function is enabled by setting the inv02 bit of invc0 register to 1. when this function is on, timer b2 is used to control the carrier wave, and timers a4, a1 and a2 are used __ ___ ___ to control three-phase pwm outputs (u, u, v, v, w and w). the dead time is controlled by a dedicated dead time timer. figure 1.16.8 shows the example of triangular modulation waveform and figure 1.16.9 shows the example of sawtooth modulation waveform.
three-phase motor control timer functions 138 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. timer b2 u phase carrier wave signal wave u phase output signal * u phase u phase output signal * u phase u phase inv14 = 0 carrier wave: sawtooth waveform inv14 = 1 transfer to three-phase output shift register rewriting idb0, idb1 registers * internal signals. see the block diagram of the three-phase motor control timer function. shown here is a typical waveform for the case where invc0= 01xx110x 2 (x = set as suitable for the system) and invc1 = 010xxx00 2 . an example for changing pwm outputs is shown below. ? ictb2=n (timer b2 interrupt is generated at every nth occurrence of a timer b2 underflow) ? initial values of idb0 and idb1 registers: du0=0, dub0=1, du1=1, dub1=1. the register values are changed to du0=1, dub0=0, du1=1, dub1=1 a timer b2 interrupt occurs. start trigger signal for timer a4* timer a4 one-shot pulse* dead time dead time (h active) (l active) figure 1.16.9. sawtooth wave modulation operation
serial i/o 139 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. serial i/o serial i/o is configured with five channels: uart0 to uart2, si/o3 and si/o4. uarti (i=0 to 2) uarti each have an exclusive timer to generate a transfer clock, so they operate independently of each other. figure 1.17.1 shows the block diagram of uarti. figures 1.17.2 shows the block diagram of the uarti transmit/receive. uarti has the following modes: ? clock synchronous serial i/o mode ? clock asynchronous serial i/o mode (uart mode). ? special mode 1 (i 2 c mode) ? special mode 2 ? special mode 3 (bus collision detection function, ie mode) : uart0, uart1 ? special mode 4 (sim mode) : uart2 figures 1.17.3 to 1.17.8 show the uarti-related registers. refer to tables listing each mode for register setting.
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r serial i/o 140 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.17.1. uarti block diagram clock synchronous type (when internal clock is selected) clock synchronous type (when external clock is selected) clock source selection internal external cts/rts disabled cts/rts selected rxd 0 1 / (n 0 +1) 1/16 1/16 1/2 u0brg register clk 0 cts 0 / rts 0 f 1sio or f 2sio f 8sio f 32sio v cc rts 0 cts 0 txd 0 (uart0) f 1sio or f 2sio 1/2 1/2 1/8 f 8sio 1/4 f 32sio f 1sio f 2sio pclk1=0 pclk1=1 clk1 to clk0 00 2 01 2 10 2 ckdir=0 ckdir=1 ckpol ckdir=0 ckdir=1 crs=1 crs=0 crd=0 crd=1 rcsp=0 rcsp=1 v cc crd=0 crd=1 rxd polarity reversing circuit main clock, pll clock, or ring oscillator clock uart reception clock synchronous type uart transmission clock synchronous type clock synchronous type (when internal clock is selected) receive clock transmit clock reception control circuit transmission control circuit transmit/ receive unit txd polarity reversing circuit clk polarity reversing circuit cts/rts disabled cts 0 from uart1 uart reception clock synchronous type rxd 1 txd 1 (uart1) 1 / (n 1 +1) 1/16 1/16 1/2 u1brg register clk 1 f 1sio or f 2sio f 8sio f 32sio clk1 to clk0 00 2 01 2 10 2 ckdir=0 ckdir=1 ckpol ckdir=0 ckdir=1 v cc crd=0 crd=1 clkmd0=0 clkmd1=0 crs=1 crs=0 rcsp=0 rcsp=1 clkmd0=1 clkmd1=1 rxd polarity reversing circuit clock source selection internal external uart transmission clock synchronous type clock synchronous type (when internal clock is selected) receive clock transmit clock reception control circuit transmission control circuit transmit/ receive unit txd polarity reversing circuit clock synchronous type (when external clock is selected) clock synchronous type (when internal clock is selected) clk polarity reversing circuit rts1 cts1 clock output pin select cts/rts disabled cts/rts disabled cts/rts selected cts 0 from uart0 cts 1 / rts 1 / cts 0 / clks 1 note: uart2 is the n-channel open-drain output. cannot be set to the cmos output. i = 0 to 2 n i : values set to the uibrg register smd2 to smd0, ckdir: uimr register's bits clk1 to clk0, ckpol, crd, crs: uic0 register's bits clkmd0, clkmd1, rcsp: ucon register's bits rxd 2 clk 2 cts 2 / rts 2 rts 2 cts 2 txd 2 (uart2) 1 / (n 2 +1) 1/16 1/16 1/2 u2brg register f 1sio or f 2sio f 8sio f 32sio clk1 to clk0 00 2 01 2 10 2 ckdir=0 ckdir=1 ckpol ckdir=0 ckdir=1 crs=1 crs=0 v cc crd=0 crd=1 reception control circuit transmission control circuit uart reception clock synchronous type uart transmission clock synchronous type clock synchronous type (when internal clock is selected) receive clock transmit clock rxd polarity reversing circuit internal external clock source selection txd polarity reversing circuit transmit/ receive unit (note) clock synchronous type (when internal clock is selected) clock synchronous type (when external clock is selected) clk polarity reversing circuit cts/rts disabled cts/rts disabled cts/rts selected
serial i/o 141 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. sp sp par 2sp 1sp uart uart (7 bits) uart (8 bits) uart(7 bits) uart (9 bits) clock synchronous type clock synchronous type data bus low-order bits txdi uarti transmit register par disabled par enabled d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 uitb register uart (8 bits) uart (9 bits) clock synchronous type uirb register uarti receive register 2sp 1sp uart (7 bits) uart (8 bits) uart(7 bits) uart (9 bits) clock synchronous type clock synchronous type rxdi uart (8 bits) uart (9 bits) data bus high-order bits d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 8 0000000 sp sp par 0 reverse no reverse error signal output circuit rxd data reverse circuit error signal output enable error signal output disable reverse no reverse logic reverse circuit + msb/lsb conversion circuit logic reverse circuit + msb/lsb conversion circuit par enabled par disabled uart clock synchronous type txd data reverse circuit i=0 to 2 sp: stop bit par: parity bit smd2 to smd0, stps, prye, iopol, ckdir: uimr register's bits uiere: uic0 register's bit iopol=1 iopol=0 stps= 0 stps= 1 prye=1 prye=0 stps= 1 stps = 0 prye=0 prye=1 iopol=1 iopol=0 uiere=1 uiere=0 figure 1.17.2. uarti transmit/receive unit
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r serial i/o 142 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.17.3. u0tb to u2tb register, u0rb to u2rb register, and u0brg to u2brg register b7 (b15) (b15) symbol address after reset u0rb 03a7 16 -03a6 16 indeterminate u1rb 03af 16 -03ae 16 indeterminate u2rb 037f 16 -037e 16 indeterminate b7 b0 (b8) b7 b0 uarti receive buffer register (i=0 to 2) function bit name bit symbol 0 : no framing error 1 : framing error found 0 : no parity error 1 : parity error found 0 : no error 1 : error found note 1: when the uimr registers smd2 to smd0 bits = 000 2 (serial i/o disabled) or the uic1 registers re bit = 0 (reception disabled), all of the sum, per, fer and oer bits are set to 0 (no error). the sum bit is set to 0 (no error) when all of the per, fer and oer bits = 0 (no error). also, the per and fer bits are set to 0 by reading the lower byte of the uirb register. note 2: the abt bit is set to 0 by writing 0 in a program. (writing 1 has no effect.) oer fer per sum overrun error flag (note 1) framing error flag (note 1) parity error flag (note 1) error sum flag (note 1) 0 : no overrun error 1 : overrun error found nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be 0. receive data (d 7 to d 0 ) abt arbitration lost detecting flag (note 2) 0 : not detected 1 : detected uarti bit rate generator (i=0 to 2)(notes 1, 2) b0 symbol address a fter reset u0brg 03a1 16 indeterminate u1brg 03a9 16 indeterminate u2brg 0379 16 indeterminate function assuming that set value = n, uibrg divides the count source by n + 1 00 16 to ff 16 setting range note 1: write to this register while serial i/o is neither transmitting nor receiving. note 2: use mov instruction to write to this register. b7 b0 (b8) b7 b0 uarti transmit buffer register (i=0 to 2)(note) function transmit data nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be indeterminate. symbol address after reset u0tb 03a3 16 -03a2 16 indeterminate u1tb 03ab 16 -03aa 16 indeterminate u2tb 037b 16 -037a 16 indeterminate rw note: use mov instruction to write to this register. wo rw rw ro ro ro ro ro (b7-b0) (b10-b9) rw wo receive data (d 8 ) ro (b8)
serial i/o 143 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. uarti transmit/receive mode register (i=0 to 2) symbol address after reset u0mr to u2mr 03a0 16 , 03a8 16 , 0378 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol rw ckdir smd1 smd0 serial i/o mode select bit (note 2) smd2 internal/external clock select bit stps pry prye iopol parity enable bit 0 : internal clock 1 : external clock (note 1) stop bit length select bit odd/even parity select bit txd, rxd i/o polarity reverse bit 0 : one stop bit 1 : two stop bits 0 : parity disabled 1 : parity enabled 0 0 0 : serial i/o disabled 0 0 1 : clock synchronous serial i/o mode 0 1 0 : i 2 c mode 1 0 0 : uart mode transfer data 7 bits long 1 0 1 : uart mode transfer data 8 bits long 1 1 0 : uart mode transfer data 9 bits long must not be set except above b2 b1 b0 effective when prye = 1 0 : odd parity 1 : even parity 0 : no reverse 1 : reverse function note 1: set the corresponding port direction bit for each clki pin to 0 (input mode). note 2: to receive data, set the corresponding port direction bit for each rxdi pin to 0 (input mode). note 3: set the corresponding port direction bit for scl and sda pins to 0 (input mode). uarti transmit/receive control register 0 (i=0 to 2) symbol address after reset u0c0 to u2c0 03a4 16 , 03ac 16 , 037c 16 00001000 2 b7 b6 b5 b4 b3 b2 b1 b0 function txept clk1 clk0 crs crd nch ckpol brg count source select bit transmit register empty flag 0 : transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : transmit data is output at rising edge of transfer clock and receive data is input at falling edge clk polarity select bit cts/rts function select bit cts/rts disable bit data output select bit (note 2) 0 0 : f 1sio or f 2sio is selected 0 1 : f 8sio is selected 1 0 : f 32sio is selected 1 1 : must not be set b1 b0 0 : lsb first 1 : msb first 0 : data present in transmit register (during transmission) 1 : no data present in transmit register (transmission completed) 0 : cts/rts function enabled 1 : cts/rts function disabled (p6 0 , p6 4 and p7 3 can be used as i/o ports) 0 : txdi/sdai and scli pins are cmos output 1 : txdi/sdai and scli pins are n-channel open-drain output uform transfer format select bit (note 3) effective when crd = 0 0 : cts function is selected (note 1) 1 : rts function is selected bit name bit symbol note 1: set the corresponding port direction bit for each ctsi pin to 0 (input mode). note 2: t x d 2 /sda 2 and scl 2 are n-channel open-drain output. cannot be set to the cmos output. set the nch bit of the u2c0 register to 0. note 3: effective for clock synchronous serial i/o mode and uart mode transfer data 8 bits long. note 4: cts 1 /rts 1 can be used when the ucon registers clkmd1 bit = 0 (only clk 1 output) and the ucon registers rcsp bit = 0 (cts 0 /rts 0 not separated). rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw ro (note 3) (note 4) figure 1.17.4. u0mr to u2mr register and u0c0 to u2c0 register
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r serial i/o 144 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. uarti transmit/receive control register 1 (i=0, 1) symbol address a fter reset u0c1, u1c1 03a5 16 ,03ad 16 00000010 2 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol rw function te ti re ri transmit enable bit receive enable bit receive complete flag transmit buffer empty flag 0 : transmission disabled 1 : transmission enabled 0 : data present in uitb register 1 : no data present in uitb register 0 : reception disabled 1 : reception enabled 0 : no data present in uirb register 1 : data present in uirb register nothing is assigned. when write, set 0. when read, these contents are 0. uart2 transmit/receive control register 1 symbol address a fter reset u2c1 037d 16 00000010 2 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol function te ti re ri transmit enable bit receive enable bit receive complete flag transmit buffer empty flag 0 : transmission disabled 1 : transmission enabled 0 : reception disabled 1 : reception enabled u2irs uart2 transmit interrupt cause select bit 0 : transmit buffer empty (ti = 1) 1 : transmit is completed (txept = 1) u2rrm uart2 continuous receive mode enable bit 0 : continuous receive mode disabled 1 : continuous receive mode enabled data logic select bit 0 : no reverse 1 : reverse u2lch u2ere error signal output enable bit 0 : output disabled 1 : output enabled data logic select bit 0 : no reverse 1 : reverse uilch uiere error signal output enable bit 0 : output disabled 1 : output enabled rw rw rw rw ro ro rw rw rw rw rw rw rw ro ro (b5-b4) 0 : data present in u2tb register 1 : no data present in u2tb register 0 : no data present in u2rb register 1 : data present in u2rb register figure 1.17.5. u0c1 to u2c1 registers
serial i/o 145 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.17.6. ucon register and u0smr to u2smr registers note: when using multiple transfer clock output pins, make sure the following conditions are met: u1mr registers ckdir bit = 0 (internal clock) uart transmit/receive control register 2 symbol address a fter reset ucon 03b0 16 x0000000 2 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol rw function clkmd0 clkmd1 uart0 transmit interrupt cause select bit uart0 continuous receive mode enable bit 0 : continuous receive mode disabled 1 : continuous receive mode enable uart1 continuous receive mode enable bit uart1 clk/clks select bit 0 uart1 transmit interrupt cause select bit 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) 0 : clk output is only clk1 1 : transfer clock output from multiple pins function selected 0 : continuous receive mode disabled 1 : continuous receive mode enabled nothing is assigned. when write, set 0. when read, its content is indeterminate. u0irs u1irs u0rrm u1rrm uart1 clk/clks select bit 1 (note) effective when clkmd1 = 1 0 : clock output from clk1 1 : clock output from clks1 uart2 special mode register (i=0 to 2) symbol address after reset u0smr to u2smr 036f 16 , 0373 16 , 0377 16 x0000000 2 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol function abscs acse sss i 2 c mode select bit bus busy flag 0 : stop condition detected 1 : start condition detected (busy) bus collision detect sampling clock select bit arbitration lost detecting flag control bit 0 : other than i 2 c mode 1 : i 2 c mode 0 : update per bit 1 : update per byte iicm abc bbs 0 : irrelevant to rxdi 1 : synchronous with rxdi (note 3) set to 0 transmit start condition select bit 0 : rising edge of transfer clock 1 : underflow signal of timer aj (note 2) auto clear function select bit of transmit enable bit 0 : no auto clear function 1 : auto clear at occurrence of bus collision note 1: the bbs bit is set to 0 by writing 0 in a program. (writing 1 has no effect.). note 2: underflow signal of timer a3 in uart0, underflow signal of timer a4 in uart1, underflow signal of timer a0 in uart2. note 3: when a transfer begins, the sss bit is set to 0 (irrelevant to rxdi). (note1) rcsp separate uart0 cts/rts bit 0 : cts/rts shared pin 1 : cts/rts separated (cts 0 supplied from the p6 4 pin) nothing is assigned. when write, set 0. when read, its content is indeterminate. rw rw rw rw rw rw rw (b7) rw rw rw rw rw rw rw rw (b7) 0 (b3) reserved bit
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r serial i/o 146 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. uarti special mode register 2 (i=0 to 2) symbol address after reset u0smr2 to u2smr2 036e 16 , 0372 16 , 0376 16 x0000000 2 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol rw function stac swc2 sdhi i c mode select bit 2 scl wait output bit 0 : disabled 1 : enabled sda output stop bit uarti initialization bit clock-synchronous bit refer to table 1.20.4 0 : disabled 1 : enabled iicm2 csc swc als 0 : disabled 1 : enabled sda output disable bit scl wait output bit 2 0: enabled 1: disabled (high impedance) 0 : disabled 1 : enabled 0: transfer clock 1: 0 output 2 uarti special mode register 3 (i=0 to 2) symbol address a fter reset u0smr3 to u2smr3 0 36d 16 , 0371 16 , 0375 16 000x0x0x 2 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol function dl2 sdai digital delay setup bit (note 1, note 2) dl0 dl1 0 0 0 : without delay 0 0 1 : 1 to 2 cycle(s) of uibrg count source 0 1 0 : 2 to 3 cycles of uibrg count source 0 1 1 : 3 to 4 cycles of uibrg count source 1 0 0 : 4 to 5 cycles of uibrg count source 1 0 1 : 5 to 6 cycles of uibrg count source 1 1 0 : 6 to 7 cycles of uibrg count source 1 1 1 : 7 to 8 cycles of uibrg count source nothing is assigned. when write, set 0. when read, its content is indeterminate. b7 b6 b5 nothing is assigned. when write, set 0. when read, its content is indeterminate. 0 : without clock delay 1 : with clock delay clock phase set bit 0 : clki is cmos output 1 : clki is n-channel open drain output clock output select bit ckph nodc note 1 : the dl2 to dl0 bits are used to generate a delay in sdai output by digital means during i 2 c mode. in other than i 2 c mode, set these bits to 000 2 (no delay). note 2 : the amount of delay varies with the load on scli and sdai pins. also, when using an external clock, the amount of delay increases by about 100 ns. rw rw rw rw rw rw rw (b7) rw rw rw rw rw rw (b0) nothing is assigned. when write, set 0. when read, its content is indeterminate. nothing is assigned. when write, set 0. when read, its content is indeterminate. (b2) (b4) figure 1.17.7. u0smr2 to u2smr2 registers and u0smr3 to u2smr3 registers
serial i/o 147 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.17.8. u0smr4 to u2smr4 registers uarti special mode register 4 (i=0 to 2) symbol address a fter reset u0smr4 to u2smr4 0 36c 16 , 0370 16 , 0374 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol rw function ackc sclhi swc9 start condition generate bit (note) stop condition generate bit (note) 0 : clear 1 : start scl,sda output select bit ack data bit restart condition generate bit (note) 0 : clear 1 : start 0 : clear 1 : start stareq rstareq stpreq ackd 0 : start and stop conditions not output 1 : start and stop conditions output scl output stop enable bit ack data output enable bit 0 : disabled 1 : enabled 0 : ack 1 : nack 0 : serial i/o data output 1 : ack data output note: set to 0 when each condition is generated. stspsel 0 : scl l hold disabled 1 : scl l hold enabled scl wait bit 3 rw rw rw rw rw rw rw rw
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r serial i/o (clock synchronous serial i/o) 148 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. clock synchronous serial i/o mode the clock synchronous serial i/o mode uses a transfer clock to transmit and receive data. table 1.18.1 lists the specifications of the clock synchronous serial i/o mode. table 1.18.2 lists the registers used in clock synchronous serial i/o mode and the register values set. item specification transfer data format ? transfer data length: 8 bits transfer clock ? uimr(i=0 to 2) registers ckdir bit = 0 (internal clock) : fj/ 2(n+1) fj = f 1sio , f 2sio , f 8sio , f 32sio . n: setting value of uibrg register 00 16 to ff 16 ? ckdir bit = 1 (external clock) : input from clki pin transmission, reception control _______ _______ _______ _______ ? selectable from cts function, rts function or cts/rts function disable transmission start condition ? before transmission can start, the following requirements must be met (note 1) _ the te bit of uic1 register= 1 (transmission enabled) _ the ti bit of uic1 register = 0 (data present in uitb register) _______ _______ _ if cts function is selected, input on the ctsi pin = l reception start condition ? before reception can start, the following requirements must be met (note 1) _ the re bit of uic1 register= 1 (reception enabled) _ the te bit of uic1 register= 1 (transmission enabled) _ the ti bit of uic1 register= 0 (data present in the uitb register) ? for transmission, one of the following conditions can be selected _ the uiirs bit (note 3) = 0 (transmit buffer empty): when transferring data from the uitb register to the uarti transmit register (at start of transmission) _ the uiirs bit =1 (transfer completed): when the serial i/o finished sending data from the uarti transmit register ? for reception when transferring data from the uarti receive register to the uirb register (at completion of reception) error detection ? overrun error (note 2) this error occurs if the serial i/o started receiving the next data before reading the uirb register and received the 7th bit of the next data select function ? clk polarity selection transfer data input/output can be chosen to occur synchronously with the rising or the falling edge of the transfer clock ? lsb first, msb first selection whether to start sending/receiving data beginning with bit 0 or beginning with bit 7 can be selected ? continuous receive mode selection reception is enabled immediately by reading the uirb register ? switching serial data logic this function reverses the logic value of the transmit/receive data ? transfer clock output from multiple pins selection (uart1) the output pin can be selected in a program from two uart1 transfer clock pins that have been set _______ _______ ? separate cts/rts pins (uart0) _________ _________ cts 0 and rts 0 are input/output from separate pins note 1: when an external clock is selected, the conditions must be met while if the uic0 registers ckpol bit = 0 interrupt request generation timing (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the external clock is in the high state; if the uic0 registers ckpol bit = 1 (transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state. note 2: if an overrun error occurs, the value of uirb register will be indeterminate. the ir bit of siric register does not change. note 3: the u0irs and u1irs bits respectively are the ucon register bits 0 and 1; the u2irs bit is the u2c1 register bit 4. table 1.18.1. clock synchronous serial i/o mode specifications
serial i/o (clock synchronous serial i/o) 149 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. table 1. 18. 2. registers to be used and settings in clock synchronous serial i/o mode register bit function uitb (note3) 0 to 7 set transmission data uirb (note3) 0 to 7 reception data can be read oer overrun error flag uibrg 0 to 7 set a transfer rate uimr (note3) smd2 to smd0 set to 001 2 ckdir select the internal clock or external clock iopol set to 0 uic0 clk1 to clk0 select the count source for the uibrg register crs _______ _______ select cts or rts to use txept transmit register empty flag crd _______ _______ enable or disable the cts or rts function nch select txdi pin output mode (note 2) ckpol select the transfer clock polarity uform select the lsb first or msb first uic1 te set this bit to 1 to enable transmission/reception ti transmit buffer empty flag re set this bit to 1 to enable reception ri reception complete flag u2irs (note 1) select the source of uart2 transmit interrupt u2rrm (note 1) set this bit to 1 to use continuous receive mode uilch set this bit to 1 to use inverted data logic uiere set to 0 uismr 0 to 7 set to 0 uismr2 0 to 7 set to 0 uismr3 0 to 2 set to 0 nodc select clock output mode 4 to 7 set to 0 uismr4 0 to 7 set to 0 ucon u0irs, u1irs select the source of uart0/uart1 transmit interrupt u0rrm, u1rrm set this bit to 1 to use continuous receive mode clkmd0 select the transfer clock output pin when clkmd1 = 1 clkmd1 set this bit to 1 to output uart1 transfer clock from two pins rcsp _________ set this bit to 1 to accept as input the uart0 cts 0 signal from the p6 4 pin 7 set to 0 note 1: set the u0c1 and u1c1 register bit 4 and bit 5 to 0. the u0irs, u1irs, u0rrm and u1rrm bits are in the ucon register. note 2: txd2 pin is n channel open-drain output. set the u2c0 register's nch bit to 0. note 3: not all register bits are described above. set those bits to 0 when writing to the registers in clock synchronous serial i/o mode. i=0 to 2
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r serial i/o (clock synchronous serial i/o) 150 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. table 1.18.3 lists the functions of the input/output pins during clock synchronous serial i/o mode. table 1.18.3 shows pin functions for the case where the multiple transfer clock output pin select function is deselected. table 1.18.4 lists the p6 4 pin functions during clock synchronous serial i/o mode. note that for a period from when the uarti operation mode is selected to when transfer starts, the txdi pin outputs an h. (if the n-channel open-drain output is selected, this pin is in a high-impedance state.) table 1.18.3. pin functions ( when not select multiple transfer clock output pin function ) pin name function method of selection txdi (i = 0 to 2) (p6 3 , p6 7 , p7 0 ) serial data output serial data input transfer clock output transfer clock input i/o port (outputs dummy data when performing reception only) rxdi (p6 2 , p6 6 , p7 1 ) clki (p6 1 , p6 5 , p7 2 ) uimr registers ckdir bit=0 uimr registers ckdir bit=1 pd6 registers pd6_1 bit=0, pd6_5 bit=0, pd7 registers pd7_2 bit=0 pd6 registers pd6_2 bit=0, pd6_6 bit=0, pd7 registers pd7_1 bit=0 (can be used as an input port when performing transmission only) uic0 registers crd bit=0 uic0 registers crs bit=0 pd6 registers pd6_0 bit=0, pd6_4 bit=0, pd7 registers pd7_3 bit=0 uic0 registers crd bit=0 uic0 registers crs bit=1 uic0 registers crd bit=1 cts input rts output ctsi/rtsi (p6 0 , p6 4 , p7 3 ) pin function bit set value u1c0 register ucon register pd6 register crd crs rcsp clkmd1 clkmd0 pd6_4 p6 4 1 0 0 input: 0, output: 1 cts 1 0 00 0 rts 1 1 00 cts 0 (note1) 0 clks 1 0 0 00 1 0 1(note 2) 1 note 1: in addition to this, set the u0c0 registers crd bit to 0 (cts 0 /rts 0 enabled) and the u0 c0 registers crs bit to 1 (rts 0 selected). note 2: when the clkmd1 bit = 1 and the clkmd0 bit = 0, the following logic levels are output: ? high if the u1c0 registers clkpol bit = 0 ? low if the u1c0 registers clkpol bit = 1 table 1.18.4. p6 4 pin functions
serial i/o (clock synchronous serial i/o) 151 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.18.1. transmit and receive operation (1) example of transmit timing (when internal clock is selected) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 tc t clk stopped pulsing because the te bit = 0 write data to the uitb register tc = t clk = 2(n + 1) / fj fj: frequency of uibrg count source (f 1sio , f 2sio , f 8sio , f 32sio ) n: value set to uibrg register i: 0 to 2 transfer clock uic1 register te bit uic1 register ti bit clki txdi h l 0 1 0 1 0 1 ctsi 0 1 stopped pulsing because ctsi = h transferred from uitb register to uarti transmit register the above timing diagram applies to the case where the register bits are set as follows: ? uimr register ckdir bit = 0 (internal clock) ? uic0 register crd bit = 0 (cts/rts enabled), crs bit = 0 (cts selected) ? uic0 register ckpol bit = 0 (transmit data output at the falling edge and receive data taken in at the rising edge of the transfer clock) ? uirs bit = 0 (an interrupt request occurs when the transmit buffer becomes empty): u0irs bit is the ucon register bit 0, u1irs bit is the ucon register bit 1, and u2irs bit is the u2c1 register bit 4 cleared to 0 when interrupt request is accepted, or cleared to 0 in a program uic0 register txept bit sitic register ir bit 1 / f ext write dummy data to uitb register uic1 register te bit uic1 register ti bit clki rxdi uic1 register ri bit rtsi h l 0 1 0 1 0 1 uic1 register re bit 0 1 receive data is taken in transferred from uitb register to uarti transmit register read out from uirb register f ext : frequency of external clock transferred from uarti receive register to uirb register sitic register ir bit 0 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 make sure the following conditions are met when input to the clki pin before receiving data is high: ? uic0 register te bit = 1 (transmit enabled) ? uic0 register re bit = 1 (receive enabled) ? write dummy data to the uitb register cleared to 0 when interrupt request is accepted, or cleared to 0 in a program the above timing diagram applies to the case where the register bits are set as follows: ? uimr register ckdir bit = 1 (external clock) ? uic0 register crd bit = 0 (cts/rts enabled), crs bit = 1 (rts selected) ? uic0 register ckpol bit = 0 (transmit data output at the falling edge and receive data taken in at the rising edge of the transfer clock) even if the reception is completed, the rts does not change. the rts becomes l when the ri bit changes to 0 from 1. (2) example of receive timing (when external clock is selected)
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r serial i/o (clock synchronous serial i/o) 152 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. (a) clk polarity select function use the uic0 register (i = 0 to 2)s ckpol bit to select the transfer clock polarity. figure 1.18.2 shows the polarity of the transfer clock. (2) when the uic0 registers ckpol bit = 1 (transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock) d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 0 t x d i r x d i clk i (1) when the uic0 registers ckpol bit = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock) d 1 d 2 d 3 d 4 d 5 d 6 d 7 d0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 t x d i r x d i clk i note 1: this applies to the case where the uic0 registers uform bit = 0 (lsb first) and uic1 register's uilch bit = 0 (no reverse). note 2: when not transferring, the clki pin outputs a high signal. note 3: when not transferring, the clki pin outputs a low signal. i = 0 to 2 (note 2) (note 3) figure 1.18.2. transfer clock polarity (b) lsb first/msb first select function use the uic0 register (i = 0 to 2)s uform bit to select the transfer format. figure 1.18.3 shows the transfer format. figure 1.18.3. transfer format (1) when uic0 register's uform bit = 0 (lsb first) d0 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 1 d 2 d 3 d 4 d 5 d 6 d 7 t x d i r x d i clk i (2) when uic0 register's uform bit = 1 (msb first) d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 t x d i r x d i clk i note: this applies to the case where the uic0 registers ckpol bit = 0 ( transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock) and the uic1 registers uilch bit = 0 (no reverse). i = 0 to 2
serial i/o (clock synchronous serial i/o) 153 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. (c) continuous receive mode when the uirrm bit (i = 0 to 2) = 1 (continuous receive mode), the uic1 registers ti bit is set to 1 (data present in the uitb register) by reading the uirb register. in this case, i.e., uirrm bit = 1, do not write dummy data to the uitb register in a program. the u0rrm and u1rrm bits are the ucon register bit 2 and bit 3, respectively, and the u2rrm bit is the u2c1 register bit 4. (d) serial data logic switching function when the uic1 register (i = 0 to 2)s uilch bit = 1 (reverse), the data written to the uitb register has its logic reversed before being transmitted. similarly, the received data has its logic reversed when read from the uirb register. figure 1.18.4 shows serial data logic. figure 1.18.4. serial data logic switching d0 d1 d2 d3 d4 d5 d6 d7 transfer clock txd i (no reverse) h l h l txd i (reverse) d0 d1 d2 d3 d4 d5 d6 d7 h l (1) when the uic1 register's uilch bit = 0 (no reverse) transfer clock h l (2) when the uic1 register's uilch bit = 1 (reverse) note: this applies to the case where the uic0 registers ckpol bit = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock) and the uform bit = 0 (lsb first). i = 0 to 2 (e) transfer clock output from multiple pins (uart1) use the ucon registers clkmd1 to clkmd0 bits to select one of the two transfer clock output pins. (see figure 1.18.5.) this function can be used when the selected transfer clock for uart1 is an internal clock. figure 1.18.5. transfer clock output from multiple pins microcomputer t x d 1 (p6 7 ) clks 1 (p6 4 ) clk 1 (p6 5 ) in clk in clk note: this applies to the case where the u1mrregister's ckdir bit = 0 (internal clock) and the ucon register's clkmd1 bit = 1 ( transfer clock out p ut from multi p le p ins ) . transfer enabled when the ucon register's clkmd0 bit = 0 transfer enabled when the ucon register's clkmd0 bit = 1
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r serial i/o (clock synchronous serial i/o) 154 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. _______ _______ (f) cts/rts separate function (uart0) _______ _______ _______ _______ this function separates cts 0 /rts 0 , outputs rts 0 from the p6 0 pin, and accepts as input the cts 0 from the p6 4 pin. to use this function, set the register bits as shown below. _______ _______ ? u0c0 register's crd bit = 0 (enables uart0 cts/rts) _______ ? u0c0 register's crs bit = 1 (outputs uart0 rts) _______ _______ ? u1c0 register's crd bit = 0 (enables uart1 cts/rts) _______ ? u1c0 register's crs bit = 0 (inputs uart1 cts) _______ ? ucon register's rcsp bit = 1 (inputs cts 0 from the p6 4 pin) ? ucon register's clkmd1 bit = 0 (clks 1 not used) _______ _______ _______ _______ note that when using the cts/rts separate function, uart1 cts/rts separate function cannot be used. _______ _______ figure 1.18.6. cts/rts separat function microcomputer t x d 0 (p6 3 ) r x d 0 (p6 2 ) in out cts rts cts 0 (p6 4 ) rts 0 (p6 0 ) ic clk 0 (p6 1 ) clk
serial i/o (uart) 155 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. item specification transfer data format ? character bit (transfer data): selectable from 7, 8 or 9 bits ? start bit: 1 bit ? parity bit: selectable from odd, even, or none ? stop bit: selectable from 1 or 2 bits transfer clock ? uimr(i=0 to 2) registers ckdir bit = 0 (internal clock) : fj/ 16(n+1) fj = f 1sio , f 2sio , f 8sio , f 32sio . n: setting value of uibrg register 00 16 to ff 16 ? ckdir bit = 1 (external clock) : f ext /16(n+1) f ext : input from clki pin. n :setting value of uibrg register 00 16 to ff 16 transmission, reception control _______ _______ _______ _______ ? selectable from cts function, rts function or cts/rts function disable transmission start condition ? before transmission can start, the following requirements must be met _ the te bit of uic1 register= 1 (transmission enabled) _ the ti bit of uic1 register = 0 (data present in uitb register) _______ _______ _ if cts function is selected, input on the ctsi pin = l reception start condition ? before reception can start, the following requirements must be met _ the re bit of uic1 register= 1 (reception enabled) _ start bit detection ? for transmission, one of the following conditions can be selected _ the uiirs bit (note 2) = 0 (transmit buffer empty): when transferring data from the uitb register to the uarti transmit register (at start of transmission) _ the uiirs bit =1 (transfer completed): when the serial i/o finished sending data from the uarti transmit register ? for reception when transferring data from the uarti receive register to the uirb register (at completion of reception) error detection ? overrun error (note 1) this error occurs if the serial i/o started receiving the next data before reading the uirb register and received the bit one before the last stop bit of the next data ? framing error this error occurs when the number of stop bits set is not detected ? parity error this error occurs when if parity is enabled, the number of 1s in parity and character bits does not match the number of 1s set ? error sum flag this flag is set (= 1) when any of the overrun, framing, and parity errors is encountered select function ? lsb first, msb first selection whether to start sending/receiving data beginning with bit 0 or beginning with bit 7 can be selected ? serial data logic switch this function reverses the logic of the transmit/receive data. the start and stop bits are not reversed. ? t x d, r x d i/o polarity switch this function reverses the polarities of hte t x d pin output and r x d pin input. the logic levels of all i/o data is reversed. _______ _______ ? separate cts/rts pins (uart0) _________ _________ cts 0 and rts 0 are input/output from separate pins note 1: if an overrun error occurs, the value of uirb register will be indeterminate. the ir bit of siric register does not change. note 2: the u0irs and u1irs bits respectively are the ucon register bits 0 and 1; the u2irs bit is the u2c1 register bit 4. clock asynchronous serial i/o (uart) mode the uart mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format. tables 1.19.1 lists the specifications of the uart mode. interrupt request generation timing table 1.19.1. uart mode specifications
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r serial i/o (uart) 156 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. table 1. 19. 2. registers to be used and settings in uart mode register bit function uitb 0 to 8 set transmission data (note 1) uirb 0 to 8 reception data can be read (note 1) oer,fer,per,sum error flag uibrg --- set a transfer rate uimr smd2 to smd0 set these bits to 100 2 when transfer data is 7 bits long set these bits to 101 2 when transfer data is 8 bits long set these bits to 110 2 when transfer data is 9 bits long ckdir select the internal clock or external clock stps select the stop bit pry, prye select whether parity is included and whether odd or even iopol select the txd/rxd input/output polarity uic0 clk0, clk1 select the count source for the uibrg register crs _______ _______ select cts or rts to use txept transmit register empty flag crd _______ _______ enable or disable the cts or rts function nch select txdi pin output mode (note 2) ckpol set to 0 uform lsb first or msb first can be selected when transfer data is 8 bits long. set this bit to 0 when transfer data is 7 or 9 bits long. uic1 te set this bit to 1 to enable transmission ti transmit buffer empty flag re set this bit to 1 to enable reception ri reception complete flag u2irs (note 2) select the source of uart2 transmit interrupt u2rrm (note 2) set to 0 uilch set this bit to 1 to use inverted data logic uiere set to 0 uismr 0 to 7 set to 0 uismr2 0 to 7 set to 0 uismr3 0 to 7 set to 0 uismr4 0 to 7 set to 0 ucon u0irs, u1irs select the source of uart0/uart1 transmit interrupt u0rrm, u1rrm set to 0 clkmd0 invalid because clkmd1 = 0 clkmd1 set to 0 rcsp _________ set this bit to 1 to accept as input the uart0 cts 0 signal from the p6 4 pin 7 set to 0 note 1: the bits used for transmit/receive data are as follows: bit 0 to bit 6 when transfer data is 7 bits long; bit 0 to bit 7 when transfer data is 8 bits long; bit 0 to bit 8 when transfer data is 9 bits long. note 2: set the u0c1 and u1c1 registers bit 4 to bit 5 to 0. the u0irs, u1irs, u0rrm and u1rrm bits are included in the ucon register. note 3: txd2 pin is n channel open-drain output. set the u2c0 register's nch bit to 0. i=0 to 2
serial i/o (uart) 157 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. table 1.19.3 lists the functions of the input/output pins during uart mode. table 1.19.4 lists the p6 4 pin functions during uart mode. note that for a period from when the uarti operation mode is selected to when transfer starts, the txdi pin outputs an h. (if the n-channel open-drain output is selected, this pin is in a high-impedance state.) table 1.19.3. i/o pin functions pin name function method of selection txdi (i = 0 to 2) (p6 3 , p6 7 , p7 0 ) serial data output serial data input input/output port transfer clock input input/output port (outputs dummy data when performing reception only) rxdi (p6 2 , p6 6 , p7 1 ) clki (p6 1 , p6 5 , p7 2 ) uimr registers ckdir bit=0 uimr registers ckdir bit=1 pd6 registers pd6_1 bit=0, pd6_5 bit=0, pd7 registers pd7_2 bit=0 pd6 registers pd6_2 bit=0, pd6_6 bit=0, pd7 registers pd7_1 bit=0 (can be used as an input port when performing transmission only) uic0 registers crd bit=0 uic0 registers crs bit=0 pd6 registers pd6_0 bit=0, pd6_4 bit=0, pd7 registers pd7_3 bit=0 uic0 registers crd bit=0 uic0 registers crs bit=1 uic0 registers crd bit=1 cts input rts output ctsi/rtsi (p6 0 , p6 4 , p7 3 ) table 1.19.4. p6 4 pin functions pin function bit set value u1c0 register ucon register pd6 register crd crs rcsp clkmd1 pd6_4 p6 4 1 0 0 input: 0, output: 1 cts 1 0000 rts 1 10 0 cts 0 (note) 0 0 0 00 1 0 note: in addition to this, set the u0c0 registers crd bit to 0 (cts 0 /rts 0 enabled) and the u0c0 registers crs bit to 1 (rts 0 selected).
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r serial i/o (uart) 158 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. start bit parity bit txdi ctsi 1 0 1 l h 0 1 tc = 16 (n + 1) / fj or 16 (n + 1) / f ext fj : frequency of uibrg count source (f 1sio , f 2sio , f 8sio , f 32sio ) f ext : frequency of uibrg count source (external clock) n : value set to uibrg i: 0 to 2 0 1 txdi 0 1 0 1 0 1 transfer clock tc 0 1 tc transfer clock d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 sp st p sp d 0 d 1 st stop bit start bit the transfer clock stops momentarily as ctsi is h when the stop bit is checked. the transfer clock starts as the transfer starts immediately ctsi changes to l. d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st sp d 8 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st d 8 d 0 d 1 st sp sp stop bit stop bit 0 sp stopped pulsing because the te bit = 0 write data to the uitb register uic1 register te bit uic1 register ti bit uic0 register txept bit sitic register ir bit transferred from uitb register to uarti transmit register the above timing diagram applies to the case where the register bits are set as follows: ? uimr register prye bit = 1 (parity enabled) ? uimr register stps bit = 0 (1 stop bit) ? uic0 register crd bit = 0 (cts/rts enabled), crs bit = 0 (cts selected) ? uirs bit = 1 (an interrupt request occurs when transmit completed): u0irs bit is the ucon register bit 0, u1irs bit is the ucon register bit 1, and u2irs bit is the u2c1 register bit 4 cleared to 0 when interrupt request is accepted, or cleared to 0 in a program uic1 register te bit uic1 register ti bit uic0 register txept bit sitic register ir bit cleared to 0 when interrupt request is accepted, or cleared to 0 in a program write data to the uitb register transferred from uitb register to uarti transmit register tc = 16 (n + 1) / fj or 16 (n + 1) / f ext fj : frequency of uibrg count source (f 1sio , f 2sio , f 8sio , f 32sio ) f ext : frequency of uibrg count source (external clock) n : value set to uibrg i: 0 to 2 the above timing diagram applies to the case where the register bits are set as follows: ? uimr register prye bit = 0 (parity disabled) ? uimr register stps bit = 1 (2 stop bits) ? uic0 register crd bit = 1 (cts/rts disabled) ? uirs bit = 0 (an interrupt request occurs when transmit buffer becomes empty): u0irs bit is the ucon register bit 0, u1irs bit is the ucon register bit 1, and u2irs bit is the u2c1 register bit 4 (1) example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit) (2) example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits) figure 1.19.1. transmit operation
serial i/o (uart) 159 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. ? example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) figure 1.19.2. receive operation d 0 start bit sampled l uibrg count source rxdi transfer clock rtsi stop bit 1 0 0 1 h l 0 1 reception triggered when transfer clock is generated by falling edge of start bit uic1 register re bit uic1 register ri bit siric register ir bit cleared to 0 when interrupt request is accepted, or cleared to 0 in a program receive data taken in d 7 d 1 transferred from uarti receive register to uirb register the above timing diagram applies to the case where the register bits are set as follows: ? uimr register prye bit = 0 (parity disabled) ? uimr register stps bit = 0 (1 stop bit) ? uic0 register crd bit = 0 (ctsi/rtsi enabled), crs bit = 1 (rtsi selected) i = 0 to 2 (a) lsb first/msb first select function as shown in figure 1.19.3, use the uic0 registers uform bit to select the transfer format. this function is valid when transfer data is 8 bits long. figure 1.19.3. transfer format (1) when uic0 register's uform bit = 0 (lsb first) (2) when uic0 register's uform bit = 1 (msb first) note: this applies to the case where the uic0 registers ckpol bit = 0 ( transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the uic1 registers uilch bit = 0 (no reverse), uimr register's stps bit = 0 (1 stop bit) and uimr register's prye bit = 1 (parity enabled). d 1 d 2 d 3 d 4 d 5 d 6 sp d0 d 1 d 2 d 3 d 4 d 5 d 6 sp d 0 t x d i r x d i clk i d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 t x d i r x d i clk i st st d 7 p d 7 p sp sp st st p p d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 st : start bit p : parity bit sp : stop bit i = 0 to 2
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r serial i/o (uart) 160 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. (c) txd and rxd i/o polarity inverse function this function inverses the polarities of the t x di pin output and r x di pin input. the logic levels of all input/output data (including the start, stop and parity bits) are inversed. figure 1.19.5 shows the t x d pin output and r x d pin input polarity inverse. figure 1.19.5. t x d and r x d i/o polarity inverse (b) serial data logic switching function the data written to the uitb register has its logic reversed before being transmitted. similarly, the received data has its logic reversed when read from the uirb register. figure 1.19.4 shows serial data logic. figure 1.19.4. serial data logic switching transfer clock h l d0 d1 d2 d3 d4 d5 d6 d7 p spst txd i (no reverse) h l txd i (reverse) spst d3 d4 d5 d6 d7 p d0 d1 d2 h l (1) when the uic1 register's uilch bit = 0 (no reverse) (2) when the uic1 register's uilch bit = 1 (reverse) transfer clock h l note: this applies to the case where the uic0 registers ckpol bit = 0 ( transmit data output at the falling edge of the transfer clock), the uic0 register's uform bit = 0 (lsb first), the uimr register's stps bit = 0 (1 stop bit) and uimr register's prye bit = 1 (parity enabled). st : start bit p : parity bit sp : stop bit i = 0 to 2 (1) when the uimr register's iopol bit = 0 (no reverse) (2) when the uimr register's iopol bit = 1 (reverse) note: this applies to the case where the uic0 register's uform bit = 0 (lsb first), the uimr register's stps bit = 0 (1 stop bit) and the uimr register's prye bit = 1 (parity enabled). st : start bit p : parity bit sp : stop bit i = 0 to 2 d0 d1 d2 d3 d4 d5 d6 d7 p spst spst d3 d4 d5 d6 d7 p d0 d1 d2 d0 d1 d2 d3 d4 d5 d6 d7 p spst h spst d3 d4 d5 d6 d7 p d0 d1 d2 transfer clock txd i (no reverse) rxd i (no reverse) transfer clock txd i (reverse) rxd i (reverse) l h l h l h l h l h l
serial i/o (uart) 161 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. _______ _______ (d) cts/rts separate function (uart0) _______ _______ _______ _______ this function separates cts 0 /rts 0 , outputs rts 0 from the p6 0 pin, and accepts as input the cts 0 from the p6 4 pin. to use this function, set the register bits as shown below. _______ _______ ? u0c0 register's crd bit = 0 (enables uart0 cts/rts) _______ ? u0c0 register's crs bit = 1 (outputs uart0 rts) _______ _______ ? u1c0 register's crd bit = 0 (enables uart1 cts/rts) _______ ? u1c0 register's crs bit = 0 (inputs uart1 cts) _______ ? ucon register's rcsp bit = 1 (inputs cts 0 from the p6 4 pin) ? ucon register's clkmd1 bit = 0 (clks 1 not used) _______ _______ _______ _______ note that when using the cts/rts separate function, uart1 cts/rts separate function cannot be used. _______ _______ figure 1.19.6. cts/rts separate function microcomputer t x d 0 (p6 3 ) r x d 0 (p6 2 ) in out cts rts cts 0 (p6 4 ) rts 0 (p6 0 ) ic
serial i/o (special modes) 162 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. special mode 1 (i 2 c mode) i 2 c mode is provided for use as a simplified i 2 c interface compatible mode. table 1.20.1 lists the speci- fications of the i 2 c mode. table 1.20.2 lists the registers used in the i 2 c mode and the register values set. figure 1.20.1 shows the block diagram for i 2 c mode. figure 1.20.2 shows scli timing. as shown in table 1.20.3, the microcomputer is placed in i 2 c mode by setting the smd2 to smd0 bits to 010 2 and the iicm bit to 1. because sdai transmit output has a delay circuit attached, sdai output does not change state until scli goes low and remains stably low. table 1.20.1. i 2 c mode specifications item specification transfer data format ? transfer data length: 8 bits transfer clock ? during master uimr(i=0 to 2) registers ckdir bit = 0 (internal clock) : fj/ 2(n+1) fj = f 1sio , f 2sio , f 8sio , f 32sio . n: setting value of uibrg register 00 16 to ff 16 ? during slave ckdir bit = 1 (external clock) : input from clki pin transmission start condition ? before transmission can start, the following requirements must be met (note 1) _ the te bit of uic1 register= 1 (transmission enabled) _ the ti bit of uic1 register = 0 (data present in uitb register) reception start condition ? before reception can start, the following requirements must be met (note 1) _ the re bit of uic1 register= 1 (reception enabled) _ the te bit of uic1 register= 1 (transmission enabled) _ the ti bit of uic1 register= 0 (data present in the uitb register) when start or stop condition is detected, acknowledge undetected, and acknowledge detected error detection ? overrun error (note 2) this error occurs if the serial i/o started receiving the next data before reading the uirb register and received the 8th bit of the next data select function ? arbitration lost timing at which the uirb registers abt bit is updated can be selected ? sdai digital delay no digital delay or a delay of 2 to 8 uibrg count source clock cycles selectable ? clock phase setting with or without clock delay selectable note 1: when an external clock is selected, the conditions must be met while the external clock is in the high state. note 2: if an overrun error occurs, the value of uirb register will be indeterminate. the ir bit of siric register does not change . interrupt request generation timing
serial i/o (special modes) 163 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. clk control falling edge detection external clock internal clock start/stop condition detection interrupt request start condition detection stop condition detection reception register bus busy transmission register arbitration noise filter sdai scli uarti d t q d t q d t q nack ack uarti uarti uarti r uarti transmit, nack interrupt request uarti receive, ack interrupt request, dma1 request iicm=1 and iicm2=0 s r q als r s swc iicm=1 and iicm2=0 iicm2=1 iicm2=1 swc2 sdhi dma0, dma1 request (uart1: dma0 only) noise filter i=0 to 2 iicm: uismr register bit iicm2: uismr2 register bit iicm=0 iicm=1 dma0 (uart0, uart2) stpsel=0 stpsel=1 stpsel=1 stpsel=0 sda stsp scl stsp ack=1 a ck=0 q port register (note) i/o port 9th bit falling edge 9th bit ackd register delay circuit this diagram applies to the case where the uimr register's smd2 to smd0 bits = 010 2 and the uismr register's iicm bit = 1. note: when the iicm bit =1, the pins can be read even if the direction bit = 1 (output). start and stop condition generation block figure 1.20.1. i 2 c mode block diagram
serial i/o (special modes) 164 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. table 1. 20. 2. registers to be used and settings in i 2 c mode (1) (continued) register bit function master slave uitb 3 0 to 7 set transmission data set transmission data uirb 3 0 to 7 reception data can be read reception data can be read 8 ack or nack is set in this bit ack or nack is set in this bit abt arbitration lost detection flag invalid oer overrun error flag overrun error flag uibrg --- set a transfer rate invalid uimr 3 smd2 to smd0 set to 010 2 set to 010 2 ckdir set to 0 set to 1 iopol set to 0 set to 0 uic0 clk1, clk0 select the count source for the uibrg invalid register crs invalid because crd = 1 invalid because crd = 1 txept transmit buffer empty flag transmit buffer empty flag crd set to 1 set to 1 nch set to 1 2 set to 1 2 ckpol set to 0 set to 0 uform set to 1 set to 1 uic1 te set this bit to 1 to enable transmission set this bit to 1 to enable transmission ti transmit buffer empty flag transmit buffer empty flag re set this bit to 1 to enable reception set this bit to 1 to enable reception ri reception complete flag reception complete flag u2irs 1 invalid invalid u2rrm 1 , set to 0 set to 0 uilch, uiere uismr iicm set to 1 set to 1 abc select the timing at which arbitration-lost invalid is detected bbs bus busy flag bus busy flag 3 to 7 set to 0 set to 0 uismr2 iicm2 refer to table 1.20.4. refer to table 1.20.4. csc set this bit to 1 to enable clock set to 0 synchronization swc set this bit to 1 to have scli output set this bit to 1 to have scli output fixed to l at the falling edge of the 9th fixed to l at the falling edge of the 9th bit of clock bit of clock als set this bit to 1 to have sdai output set to 0 stopped when arbitration-lost is detected stac set to 0 set this bit to 1 to initialize uarti at start condition detection swc2 set this bit to 1 to have scli output s et this bit to 1 to have scli output forcibly pulled low forcibly pulled low sdhi set this bit to 1 to disable sdai output set this bit to 1 to disable sdai output 7 set to 0 set to 0 uismr3 0, 2, 4 and nodc set to 0 set to 0 ckph refer to table 1.20.4 refer to table 1.20.4 dl2 to dl0 set the amount of sdai digital delay set the amount of sdai digital delay i=0 to 2 notes: 1. set the u0c1 and u1c1 register bit 4 and bit 5 to 0. the u0irs, u1irs, u0rrm and u1rrm bits are in the ucon register. 2. txd2 pin is n channel open-drain output. set the nch bit in the u2c0 register to 0. 3. not all register bits are described above. set those bits to 0 when writing to the registers in i 2 c mode.
serial i/o (special modes) 165 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. uismr4 stareq set this bit to 1 to generate start set to 0 condition rstareq set this bit to 1 to generate restart set to 0 condition stpreq set this bit to 1 to generate stop set to 0 condition stspsel set this bit to 1 to output each condition set to 0 ackd select ack or nack select ack or nack ackc set this bit to 1 to output ack data set this bit to 1 to output ack data sclhi set this bit to 1 to have scli output set to 0 stopped when stop condition is detected swc9 set to 0 set this bit to 1 to set the scli to l hold at the falling edge of the 9th bit of clock ifsr2a ifsr26, isfr27 set to 1 set to 1 ucon u0irs, u1irs invalid invalid 2 to 7 set to 0 set to 0 register bit function master slave table 1. 20. 3. registers to be used and settings in i 2 c mode (2) (continued) i=0 to 2
serial i/o (special modes) 166 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. function i 2 c mode (smd2 to smd0 = 010 2 , iicm = 1) clock synchronous serial i/o mode (smd2 to smd0 = 001 2 , iicm = 0) factor of interrupt number 15, 17 and 19 (note 1)( refer to fig 1.20.2) no acknowledgment detection (nack) rising edge of scli 9th bit factor of interrupt number 16, 18 and 20 (note 1)( refer to fig 1.20.2) start condition detection or stop condition detection (refer to fig 1.20.4) uarti transmission output delay functions of p6 3 , p6 7 and p7 0 pins noise filter width read rxdi and scli pin levels factor of interrupt number 6, 7 and 10 (note 1)(refer to fig 1.20.2) acknowledgment detection (ack) rising edge of scli 9th bit initial value of txdi and sdai outputs uarti transmission transmission started or completed (selected by uiirs) uarti reception when 8th bit received ckpol = 0 (rising edge) ckpol = 1 (falling edge) not delayed txdi output rxdi input clki input or output selected 15ns possible when the corresponding port direction bit = 0 ckpol = 0 (h) ckpol = 1 (l) delayed sdai input/output scli input/output (cannot be used in i 2 c mode) initial and end values of scli h 200ns always possible no matter how the corresponding port direction bit is set the value set in the port register before setting i 2 c mode (note 2) timing for transferring data from the uart reception shift register to the uirb register iicm2 = 0 (nack/ack interrupt) iicm2 = 1 (uart transmit/ receive interrupt) ckph = 1 (clock delay) ckph = 1 (clock delay) uarti transmission rising edge of scli 9th bit uarti transmission falling edge of scli next to the 9th bit uarti transmission falling edge of scli 9th bit ckpol = 0 (rising edge) ckpol = 1 (falling edge) rising edge of scli 9th bit falling edge of scli 9th bit falling and rising edges of scli 9th bit functions of p6 2 , p6 6 and p7 1 pins functions of p6 1 , p6 5 and p7 2 pins i = 0 to 2 note 1: to change the interrupt sources from one to another, follow the procedure described below. 1. disable the interrupt of the corresponding interrupt number to be changed. 2. change interrupt sources from one to another. 3. set the ir bit for the corresponding interrupt number to 0 (no interrupt request). 4. set the ipl2 to ipl0 bits for the corresponding interrupt number. note 2: set the initial value of sdai output while the uimr registers smd2 to smd0 bits = 000 2 (serial i/o disabled). note 3: second data transfer to uirb register (rising edge of scli 9th bit) note 4. first data transfer to uirb register (falling edge of scli 9th bit) dma1 factor (refer to fig 1.20.2) uarti reception acknowledgment detection (ack) uarti reception falling edge of scli 9th bit store received data 1st to 8th bits are stored in uirb register bit 0 to bit 7 1st to 8th bits are stored in uirb register bit 7 to bit 0 1st to 7th bits are stored in uirb register bit 6 to bit 0, with 8th bit stored in uirb register bit 8 l read uirb register bit 6 to bit 0 as bit 7 to bit 1, and bit 8 as bit 0 (note 4) read received data uirb register status is read directly as is ckph = 0 (no clock delay) ckph = 0 (no clock delay) hl 1st to 8th bits are stored in uirb register bit 7 to bit 0 (note 3) table 1.20.4. i 2 c mode functions
serial i/o (special modes) 167 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.20.2. transfer to uirb register and interrupt timing (3) iicm2= 1 (uart transmit/receive interrupt), ckph= 0 (1) iicm2= 0 (ack and nack interrupts), ckph= 0 (no clock delay) i=0 to 2 this diagram applies to the case where the following condition is met. ? uimr register ckdir bit = 0 (slave selected) ack interrupt (dma1 request), nack interrupt transfer to uirb register receive interrupt (dma1 request) transmit interrupt transfer to uirb register (4) iicm2= 1, ckph= 1 d 6 d 5 d 4 d 3 d 2 d 1 d7 sdai scli d 0 d 6 d 5 d 4 d 3 d 2 d 1 d7 sdai scli d 0 d 6 d 5 d 4 d 3 d 2 d 1 d 8 (ack, nack) d7 sdai scli d 0 d 8 (ack, nack) d 8 (ack, nack) d 6 d 5 d 4 d 3 d 2 d 1 d 8 (ack, nack) d7 sdai scli d 0 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit b15 ??? b9 b8 b7 b0 d8 d7 d6 d5 d4 d3 d2 d1 d0 uirb register b15 ??? b9 b8 b7 b0 d8 d7 d6 d5 d4 d3 d2 d1 d0 b15 ??? b9 b8 b7 b0 d0 d7 d6 d5 d4 d3 d2 d1 b15 ??? b9 b8 b7 b0 d0 d7 d6 d5 d4 d3 d2 d1 b15 ??? b9 b8 b7 b0 d8 d7 d6 d5 d4 d3 d2 d1 d0 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit 1st bit 2nd bit 3rd bit 4 th bit 5th bit 6 th bit 7th bit 8th bit 9 th bit 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit (2) iicm2= 0, ckph= 1 (clock delay) ack interrupt (dma1 request), nack interrupt transfer to uirb register uirb register transmit interrupt transfer to uirb register receive interrupt (dma1 request) transfer to uirb register uirb register uirb register uirb register
serial i/o (special modes) 168 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. detection of start and stop condtion whether a start or a stop condition has been detected is determined. a start condition-detected interrupt request is generated when the sdai pin changes state from high to low while the scli pin is in the high state. a stop condition-detected interrupt request is generated when the sdai pin changes state from low to high while the scli pin is in the high state. because the start and stop condition-detected interrupts share the interrupt control register and vec- tor, check the uismr registers bbs bit to determine which interrupt source is requesting the interrupt. figure 1.20.3. detection of start and stop condition output of start and stop condition a start condition is generated by setting the uismr4 register (i = 0 to 2)s stareq bit to 1 (start). a restart condition is generated by setting the uismr4 registers rstareq bit to 1 (start). a stop condition is generated by setting the uismr4 registers stpreq bit to 1 (start). a start condition is output by setting the stareq bit to 1 and then the uismr4 registers stspsel bit to 1 (start). similarly, a restart condition is output by setting the rstareq bit to 1 and then the stspsel bit to 1, and a stop condition is output by setting the stpreq bit to 1 and then the stspsel bit to 1. table 1.20.5 and figure 1.20.4 show the functions of the stspsel. if start, stop and restart conditions are to be output, make sure no interrupts will occur between the instruction that sets the stareq, stpreq or rstareq bit to 1 and the instruction that sets the stspsel bit to 1. also, if a start condition is to be output, make sure the stareq bit is set to 1 before setting the stspsel bit to 1. 3 to 6 cycles < duration for setting-up (note) 3 to 6 cycles < duration for holding (note) i = 0 to 2 note: when the pclkr register's pclk1 bit = 1, this is the cycle number of f 1sio , and the pclk1 bit = 0, this is the cycle number of f 2sio . duration for setting up duration for holding scli sdai (start condition) sda i (stop condition)
serial i/o (special modes) 169 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. table 1.20.5. stspsel bit functions figure 1.20.4. stspsel bit functions function output of scli and sdai pins star/stop condition interrupt request generation timing stspsel = 0 output of transfer clock and data output of start/stop condition is accomplished by a program using ports (not automatically generated in hardware) start/stop condition detection stspsel = 1 output of a start/stop condition according to the stareq, rstareq and stpreq bit finish generating start/stop condi- tion start condition detection interrupt stop condition detection interrupt (1) when slave ckdir=1 (external clock) start condition detection interrupt stop condition detection interrupt (2) when master ckdir=0 (internal clock), ckph=1 (clock delayed) sdai scli set stareq= 1 (start) set stpreq= 1 (start) stpsel bit 0 sdai scli stpsel bit set to 1 in a program set to 0 in a program set to 1 in a program set to 0 in a program 1st 2nd 3rd 4th 5th 6th 7th 8th 9th bit 1st 2nd 3rd 4th 5th 6th 7th 8th 9th bit arbitration unmatching of the transmit data and sdai pin input data is checked synchronously with the rising edge of scli. use the uismr registers abc bit to select the timing at which the uirb registers abt bit is updated. if the abc bit = 0 (updated bitwise), the abt bit is set to 1 at the same time unmatching is detected during check, and is cleared to 0 when not detected. in cases when the abc bit is set to 1, if unmatching is detected even once during check, the abt bit is set to 1 (unmatching detected) at the falling edge of the clock pulse of 9th bit. if the abt bit needs to be updated bytewise, clear the abt bit to 0 (undetected) after detecting acknowledge in the first byte, before transferring the next byte. setting the uismr2 registers als bit to 1 (sda output stop enabled) causes arbitration-lost to occur, in which case the sdai pin is placed in the high-impedance state at the same time the abt bit is set to 1 (unmatching detected).
serial i/o (special modes) 170 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. transfer clock data is transmitted/received using a transfer clock like the one shown in figure 1.20.4. the uismr2 registers csc bit is used to synchronize the internally generated clock (internal scli) and an external clock supplied to the scli pin. in cases when the csc bit is set to 1 (clock synchro- nization enabled), if a falling edge on the scli pin is detected while the internal scli is high, the internal scli goes low, at which time the uibrg register value is reloaded with and starts counting in the low-level interval. if the internal scli changes state from low to high while the scli pin is low, counting stops, and when the scli pin goes high, counting restarts. in this way, the uarti transfer clock is comprised of the logical product of the internal scli and scli pin signal. the transfer clock works from a half period before the falling edge of the internal scli 1st bit to the rising edge of the 9th bit. to use this function, select an internal clock for the transfer clock. the uismr2 registers swc bit allows to select whether the scli pin should be fixed to or freed from low-level output at the falling edge of the 9th clock pulse. if the uismr4 registers sclhi bit is set to 1 (enabled), scli output is turned off (placed in the high- impedance state) when a stop condition is detected. setting the uismr2 registers swc2 bit = 1 (0 output) makes it possible to forcibly output a low-level signal from the scli pin even while sending or receiving data. clearing the swc2 bit to 0 (transfer clock) allows the transfer clock to be output from or supplied to the scli pin, instead of outputting a low-level signal. if the uismr4 registers swc9 bit is set to 1 (scl hold low enabled) when the uismr3 registers ckph bit = 1, the scli pin is fixed to low-level output at the falling edge of the clock pulse next to the ninth. setting the swc9 bit = 0 (scl hold low disabled) frees the scli pin from low-level output. sda output the data written to the uitb register bit 7 to bit 0 (d 7 to d 0 ) is sequentially output beginning with d 7 . the ninth bit (d 8 ) is ack or nack. the initial value of sdai transmit output can only be set when iicm = 1 (i 2 c mode) and the uimr registers smd2 to smd0 bits = 000 2 (serial i/o disabled). the uismr3 registers dl2 to dl0 bits allow to add no delays or a delay of 2 to 8 uibrg count source clock cycles to sdai output. setting the uismr2 registers sdhi bit = 1 (sda output disabled) forcibly places the sdai pin in the high-impedance state. do not write to the sdhi bit synchronously with the rising edge of the uarti transfer clock. this is because the abt bit may inadvertently be set to 1 (detected). sda input when the iicm2 bit = 0, the 1st to 8th bits (d 7 to d 0 ) of received data are stored in the uirb register bit 7 to bit 0. the 9th bit (d 8 ) is ack or nack. when the iicm2 bit = 1, the 1st to 7th bits (d 7 to d 1 ) of received data are stored in the uirb register bit 6 to bit 0 and the 8th bit (d 0 ) is stored in the uirb register bit 8. even when the iicm2 bit = 1, providing the ckph bit = 1, the same data as when the iicm2 bit = 0 can be read out by reading the uirb register after the rising edge of the corresponding clock pulse of 9th bit.
serial i/o (special modes) 171 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. ack and nack if the stspsel bit in the uismr4 register is set to 0 (start and stop conditions not generated) and the ackc bit in the uismr4 register is se to 1 (ack data output), the value of the ackd bit in the uismr4 register is output from the sdai pin. if the iicm2 bit = 0, a nack interrupt request is generated if the sdai pin remains high at the rising edge of the 9th bit of transmit clock pulse. an ack interrupt request is generated if the sdai pin is low at the rising edge of the 9th bit of transmit clock pulse. if acki is selected for the cause of dma1 request, a dma transfer can be activated by detection of an acknowledge. initialization of transmission/reception if a start condition is detected while the stac bit = 1 (uarti initialization enabled), the serial i/o operates as described below. - the transmit shift register is initialized, and the content of the uitb register is transferred to the transmit shift register. in this way, the serial i/o starts sending data synchronously with the next clock pulse applied. however, the uarti output value does not change state and remains the same as when a start condition was detected until the first bit of data is output synchronously with the input clock. - the receive shift register is initialized, and the serial i/o starts receiving data synchronously with the next clock pulse applied. - the swc bit is set to 1 (scl wait output enabled). consequently, the scli pin is pulled low at the falling edge of the ninth clock pulse. note that when uarti transmission/reception is started using this function, the ti does not change state. note also that when using this function, the selected transfer clock should be an external clock.
serial i/o (special modes) 172 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. special mode 2 multiple slaves can be serially communicated from one master. synchronous clock polarity and phase are selectable. table 1.20.6 lists the specifications of special mode 2. table 1.20.7 lists the registers used in special mode 2 and the register values set. figure 1.20.5 shows communication control example for special mode 2. table 1.20.6. special mode 2 specifications item specification transfer data format ? transfer data length: 8 bits transfer clock ? master mode uimr(i=0 to 2) registers ckdir bit = 0 (internal clock) : fj/ 2(n+1) fj = f 1sio , f 2sio , f 8sio , f 32sio . n: setting value of uibrg register 00 16 to ff 16 ? slave mode ckdir bit = 1 (external clock selected) : input from clki pin transmit/receive control controlled by input/output ports transmission start condition ? before transmission can start, the following requirements must be met (note 1) _ the te bit of uic1 register= 1 (transmission enabled) _ the ti bit of uic1 register = 0 (data present in uitb register) reception start condition ? before reception can start, the following requirements must be met (note 1) _ the re bit of uic1 register= 1 (reception enabled) _ the te bit of uic1 register= 1 (transmission enabled) _ the ti bit of uic1 register= 0 (data present in the uitb register) ? for transmission, one of the following conditions can be selected _ the uiirs bit of uic1 register = 0 (transmit buffer empty): when transferring data from the uitb register to the uarti transmit register (at start of transmission) _ the uiirs bit =1 (transfer completed): when the serial i/o finished sending data from the uarti transmit register ? for reception when transferring data from the uarti receive register to the uirb register (at completion of reception) error detection ? overrun error (note 2) this error occurs if the serial i/o started receiving the next data before reading the uirb register and received the 7th bit of the next data select function ? clock phase setting selectable from four combinations of transfer clock polarities and phases note 1: when an external clock is selected, the conditions must be met while if the uic0 registers ckpol bit = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the external clock is in the high state; if the uic0 registers ckpol bit = 1 (transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state. note 2: if an overrun error occurs, the value of uirb register will be indeterminate. the ir bit of siric register does not change. interrupt request generation timing
serial i/o (special modes) 173 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. p1 3 p1 2 p7 0( txd 2 ) p7 2( clk 2 ) p7 1( rxd 2 ) p9 3 p7 0( txd 2 ) p7 2( clk 2 ) p7 1( rxd 2 ) p9 3 p7 0( txd 2 ) p7 2( clk 2 ) p7 1( rxd 2 ) microcomputer (master) microcomputer (slave) microcomputer (slave) figure 1.20.5. serial bus communication control example (uart2)
serial i/o (special modes) 174 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. table 1. 20. 7. registers to be used and settings in special mode 2 register bit function uitb (note3) 0 to 7 set transmission data uirb (note3) 0 to 7 reception data can be read oer overrun error flag uibrg 0 to 7 set a transfer rate uimr (note3) smd2 to smd0 set to 001 2 ckdir set this bit to 0 for master mode or 1 for slave mode iopol set to 0 uic0 clk1, clk0 select the count source for the uibrg register crs invalid because crd = 1 txept transmit register empty flag crd set to 1 nch select txdi pin output format(note 2) ckpol clock phases can be set in combination with the uismr3 register's ckph bit uform set to 0 uic1 te set this bit to 1 to enable transmission ti transmit buffer empty flag re set this bit to 1 to enable reception ri reception complete flag u2irs (note 1) select uart2 transmit interrupt cause u2rrm(note 1), set to 0 u2lch, uiere uismr 0 to 7 set to 0 uismr2 0 to 7 set to 0 uismr3 ckph clock phases can be set in combination with the uic0 register's ckpol bit nodc set to 0 0, 2, 4 to 7 set to 0 uismr4 0 to 7 set to 0 ucon u0irs, u1irs select uart0 and uart1 transmit interrupt cause u0rrm, u1rrm set to 0 clkmd0 invalid because clkmd1 = 0 clkmd1, rcsp, 7 set to 0 note 1: set the u0c0 and u1c1 register bit 4 and bit 5 to 0. the u0irs, u1irs, u0rrm and u1rrm bits are in the ucon register. note 2: txd2 pin is n channel open-drain output. set the u2c0 register's nch bit to 0. note 3: not all register bits are described above. set those bits to 0 when writing to the registers in special mode 2. i = 0 to 2
serial i/o (special modes) 175 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. clock phase setting function one of four combinations of transfer clock phases and polarities can be selected using the uismr3 registers ckph bit and the uic0 registers ckpol bit. make sure the transfer clock polarity and phase are the same for the master and salves to be commu- nicated. (a) master (internal clock) figure 1.20.6 shows the transmission and reception timing in master (internal clock). (b) slave (external clock) figure 1.20.7 shows the transmission and reception timing (ckph=0) in slave (external clock) while figure 1.20.8 shows the transmission and reception timing (ckph=1) in slave (external clock). data output timing data input timing d 0 d 1 d 2 d 3 d 4 d 6 d 7 d 5 clock output (ckpol=0, ckph=0) "h" "l" clock output (ckpol=1, ckph=0) "h" "l" clock output (ckpol=0, ckph=1) "h" "l" clock output (ckpol=1, ckph=1) "h" "l" "h" "l" figure 1.20.6. transmission and reception timing in master mode (internal clock)
serial i/o (special modes) 176 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.20.7. transmission and reception timing (ckph=0) in slave mode (external clock) figure 1.20.8. transmission and reception timing (ckph=1) in slave mode (external clock) slave control input clock input (ckpol=0, ckph=0) clock input (ckpol=1, ckph=0) data output timing data input timing "h" "l" "h" "l" "h" "l" "h" "l" d 0 d 1 d 2 d 3 d 4 d 6 d 7 d 5 indeterminate note :uart2 output is an n-channel open drain and must be pulled-up externally. (note) clock input (ckpol=0, ckph=1) clock input (ckpol=1, ckph=1) data output timing data input timing "h" "l" "h" "l" "h" "l" "h" "l" d 0 d 1 d 2 d 3 d 6 d 7 d 4 d 5 note :uart2 output is an n-channel open drain and must be pulled-up externally. (note) slave control input
serial i/o (special modes) 177 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. special mode 3 (ie mode) in this mode, one bit of iebus is approximated with one byte of uart mode waveform. table 1.20.8 lists the registers used in ie mode and the register values set. figure 1.20.9 shows the functions of bus collision detect function related bits. if the txdi pin (i = 0 to 2) output level and rxdi pin input level do not match, a uarti bus collision detect interrupt request is generated. use the ifsr2a registers ifsr26 and ifsr27 bits to enable the uart0/uart1 bus collision detect function. table 1. 20. 8. registers to be used and settings in ie mode register bit function uitb 0 to 8 set transmission data uirb (note3) 0 to 8 reception data can be read oer,fer,per,sum error flag uibrg --- set a transfer rate uimr smd2 to smd0 set to 110 2 ckdir select the internal clock or external clock stps set to 0 pry invalid because prye=0 prye set to 0 iopol select the txd/rxd input/output polarity uic0 clk1, clk0 select the count source for the uibrg register crs invalid because crd=1 txept transmit register empty flag crd set to 1 nch select txdi pin output mode (note 2) ckpol set to 0 uform set to 0 uic1 te set this bit to 1 to enable transmission ti transmit buffer empty flag re set this bit to 1 to enable reception ri reception complete flag u2irs (note 1) select the source of uart2 transmit interrupt uirrm (note 1), set to 0 uilch, uiere uismr 0 to 3, 7 set to 0 abscs select the sampling timing at which to detect a bus collision acse set this bit to 1 to use the auto clear function of transmit enable bit sss select the transmit start condition uismr2 0 to 7 set to 0 uismr3 0 to 7 set to 0 uismr4 0 to 7 set to 0 ifsr2a ifsr26, ifsr27 set to 1 ucon u0irs, u1irs select the source of uart0/uart1 transmit interrupt u0rrm, u1rrm set to 0 clkmd0 invalid because clkmd1 = 0 clkmd1,rcsp,7 set to 0 note 1: set the u0c0 and u1c1 registers bit 4 and bit 5 to 0. the u0irs, u1irs, u0rrm and u1rrm bits are in the ucon register. note 2: txd2 pin is n channel open-drain output. set the u2c0 register's nch bit to 0. note 3: not all register bits are described above. set those bits to 0 when writing to the registers in iemode. i= 0 to 2
serial i/o (special modes) 178 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. (2) uismr register acse bit (auto clear of transmit enable bit) (1) uismr register abscs bit (bus collision detect sampling clock select) if abscs=0, bus collision is determined at the rising edge of the transfer clock transfer clock timer aj (3) uismr register sss bit (transmit start condition select) transmission enable condition is met if sss bit = 1, the serial i/o starts sending data at the rising edge (note 1) of rxdi txdi clki txdi rxdi txdi rxdi st d0 d1 d2 d3 d4 d5 d6 d7 d8 sp input to taj in if abscs=1, bus collision is determined when timer aj (one-shot timer mode) underflows. txdi rxdi st d0 d1 d2 d3 d4 d5 d6 d7 d8 sp st d0 d1 d2 d3 d4 d5 d6 d7 d8 sp st d0 d1 d2 d3 d4 d5 d6 d7 d8 sp (i=0 to 2) timer aj: timer a3 when uart0; timer a4 when uart1; timer a0 when uart2 transfer clock uibcnic register ir bit (note) uic1 register te bit note: bcnic register when uart2. if acse bit = 1 (automatically clear when bus collision occurs), the te bit is cleared to 0 (transmission disabled) when the uibcnic registers ir bit = 1 (unmatching detected). if sss bit = 0, the serial i/o starts sending data one transfer clock cycle after the transmission enable condition is met. transfer clock (note 2) note 1: the falling edge of rxdi when iopol=0; the rising edge of rxdi when iopol =1. note 2: the transmit condition must be met before the falling edge (note 1) of rxd. this diagram applies to the case where iopol=1 (reversed). figure 1.20.9. bus collision detect function-related bits
serial i/o (special modes) 179 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. item specification transfer data format ? direct format ? inverse format transfer clock ? u2mr registers ckdir bit = 0 (internal clock) : fi/ 16(n+1) fi = f 1sio , f 2sio , f 8sio , f 32sio . n: setting value of u2brg register 00 16 to ff 16 ? ckdir bit = 1 (external clock) : f ext /16(n+1) f ext : input from clk 2 pin. n: setting value of u2brg register 00 16 to ff 16 transmission start condition ? before transmission can start, the following requirements must be met _ the te bit of u2c1 register= 1 (transmission enabled) _ the ti bit of u2c1 register = 0 (data present in u2tb register) reception start condition ? before reception can start, the following requirements must be met _ the re bit of u2c1 register= 1 (reception enabled) _ start bit detection ? for transmission when the serial i/o finished sending data from the u2tb transfer register (u2irs bit =1) ? for reception when transferring data from the uart2 receive register to the u2rb register (at completion of reception) error detection ? overrun error (note) this error occurs if the serial i/o started receiving the next data before reading the u2rb register and received the bit one before the last stop bit of the next data ? framing error this error occurs when the number of stop bits set is not detected ? parity error during reception, if a parity error is detected, parity error signal is output from the txd 2 pin. during transmission, a parity error is detected by the level of input to the r x d 2 pin when a transmission interrupt occurs ? error sum flag this flag is set (= 1) when any of the overrun, framing, and parity errors is encountered note: if an overrun error occurs, the value of u2rb register will be indeterminate. the ir bit of s2ric register does not change. special mode 4 (sim mode) (uart2) based on uart mode, this is an sim interface compatible mode. direct and inverse formats can be implemented, and this mode allows to output a low from the txd2 pin when a parity error is detected. tables 1.20.9 lists the specifications of sim mode. table 1.20.10 lists the registers used in the sim mode and the register values set. table 1.20.9. sim mode specifications interrupt request generation timing
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r serial i/o (special modes) 180 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. table 1. 20. 10. registers to be used and settings in sim mode register bit function u2tb (note) 0 to 7 set transmission data u2rb (note) 0 to 7 reception data can be read oer,fer,per,sum error flag u2brg --- set a transfer rate u2mr smd2 to smd0 set to 101 2 ckdir select the internal clock or external clock stps set to 0 pry set this bit to 1 for direct format or 0 for inverse format prye set to 1 iopol set to 0 u2c0 clk1, clk0 select the count source for the u2brg register crs invalid because crd=1 txept transmit register empty flag crd set to 1 nch set to 0 ckpol set to 0 uform set this bit to 0 for direct format or 1 for inverse format u2c1 te set this bit to 1 to enable transmission ti transmit buffer empty flag re set this bit to 1 to enable reception ri reception complete flag u2irs set to 1 u2rrm set to 0 u2lch set this bit to 0 for direct format or 1 for inverse format u2ere set to 1 u2smr (note) 0 to 3 set to 0 u2smr2 0 to 7 set to 0 u2smr3 0 to 7 set to 0 u2smr4 0 to 7 set to 0 note: not all register bits are described above. set those bits to 0 when writing to the registers in sim mode.
serial i/o (special modes) 181 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.20.10. transmit and receive timing in sim mode transfer clock an l level is output from txd 2 due to the occurrence of a parity error read the u2rb register cleared to 0 when interrupt request is accepted, or cleared to 0 in a program u2c1 register te bit d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p 0 1 0 1 0 1 0 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp tc sp d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p txd 2 0 1 0 1 0 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp tc sp d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp sp d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp sp txd 2 rxd 2 pin level u2c1 register ti bit parity error signal sent back from receiver (note) u2c0 register txept bit s2tic register ir bit start bit parity bit stop bit write data to u2tb register transferred from u2tb register to uart2 transmit register an l level returns due to the occurrence of a parity error. the level is detected by the interrupt routine. the level is detected by the interrupt routine. the ir bit is set to 1 at the falling edge of transfer clock note : because txd 2 and rxd 2 are connected, this is composite waveform consisting of the transmitter's transmit waveform and the parity error signal received. note : because txd 2 and rxd 2 are connected, this is composite waveform consisting of the txd 2 output and the parity error signal sent back from receiver. tc = 16 (n + 1) / fi or 16 (n + 1) / f ext fi : frequency of u2brg count source (f 1sio , f 2sio , f 8sio , f 32sio ) f ext : frequency of u2brg count source (external clock) n : value set to u2brg the above timing diagram applies to the case where data is received in direct format. ? u2mr register pry bit = 1 (even) ? u2c0 register uform bit = 0 (lsb first) ? u2c1 register u2lch bit = 0 (no reverse) tc = 16 (n + 1) / fi or 16 (n + 1) / f ext fi : frequency of u2brg count source (f 1sio , f 2sio , f 8sio , f 32sio ) f ext : frequency of u2brg count source (external clock) n : value set to u2brg the above timing diagram applies to the case where data is transferred in the direct format. ? u2mr register pry bit = 1 (even) ? u2c0 register uform bit = 0 (lsb first) ? u2c1 register u2lch bit = 0 (no reverse) start bit parity bit stop bit cleared to 0 when interrupt request is accepted, or cleared to 0 in a program read the u2rb register (1) transmission transfer clock u2c1 register re bit rxd 2 pin level transmitter's transmit waveform (note) u2c0 register ri bit s2ric register ir bit (1) reception
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r serial i/o (special modes) 182 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.20.11 shows the example of connecting the sim interface. connect t x d 2 and r x d 2 and apply pull-up. figure 1.20.11. sim interface connection microcomputer sim card txd 2 rxd 2 (a) parity error signal output the parity error signal is enabled by setting the u2c1 registers u2ere bit to 1. ? when receiving the parity error signal is output when a parity error is detected while receiving data. this is achieved by pulling the txd2 output low with the timing shown in figure 1.20.12. if the r2rb register is read while outputting a parity error signal, the per bit is cleared to 0 and at the same time the txd2 output is returned high. ? when transmitting a transmission-finished interrupt request is generated at the falling edge of the transfer clock pulse that immediately follows the stop bit. therefore, whether a parity signal has been returned can be determined by reading the port that shares the rxd2 pin in a transmission-finished interrupt service routine. figure 1.20.12. parity error signal output timing st : start bit p : even parity sp : stop bit d0 d1 d2 d3 d4 d5 d6 d7 p spst (note) transfer clock rxd 2 txd 2 u2c1 register ri bit h l h l h l 1 0 this timing diagram applies to the case where the direct format is implemented. note: the output of microcomputer is in the high-impedance state (pulled up externally).
serial i/o (special modes) 183 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. (b) format ? direct format set the u2mr register's pry bit to 1, u2c0 register's uform bit to 0 and u2c1 register's u2lch bit to 0. ? inverse format set the pry bit to 0, uform bit to 1 and u2lch bit to 1. figure 1.20.13 shows the sim interface format. figure 1.20.13. sim interface format p : even parity d0 d1 d2 d3 d4 d5 d6 d7 p transfer clcck txd 2 txd 2 d7 d6 d5 d4 d3 d2 d1 d0 p transfer clcck (1) direct format h l h l (2) inverse format p : odd parity h l h l
184 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. si/o3, si/o4 si/o3 and si/o4 si/o3 and si/o4 are exclusive clock-synchronous serial i/os. figure 1.21.1 shows the block diagram of si/o3 and si/o4, and figure 1.21.2 shows the si/o3 and si/o4- related registers. table 1.21.1 shows the specifications of si/o3 and si/o4. figure 1.21.1. si/o3 and si/o4 block diagram data bus si/oi interrupt request note: i = 3, 4. n = a value set in the sibrg register. sitrr register si/o counter i 8 smi5 lsb msb smi2 smi3 smi3 smi6 smi1 to smi0 clk i s outi s ini sibrg register smi6 1/(n+1) 1/2 1/2 main clock, pll clock, or ring oscillator clock f 1sio 1/2 1/8 1/4 f 8sio f 32sio f 2sio pclk1=0 pclk1=1 smi4 00 2 01 2 10 2 clock source select synchronous circuit clk polarity reversing circuit
185 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. si/o3, si/o4 si/oi bit rate generator (i = 3, 4) (notes 1, 2) b7 b0 symbol address after reset s3brg 0 363 16 indeterminate s4brg 0 367 16 indeterminate description assuming that set value = n, brgi divides the count source by n + 1 00 16 to ff 16 setting range rw si/oi transmit/receive register (i = 3, 4) (note 1, 2) b7 b0 symbol address after reset s3trr 0360 16 indeterminate s4trr 0364 16 indeterminate description transmission/reception starts by writing transmit data to this register. after transmission/reception finishes, reception data can be read by reading this register. note 1: write to this register while serial i/o is neither transmitting nor receiving. note 2: to receive data, set the corresponding port direction bit for s in i to 0 (input mode). s i/oi control register (i = 3, 4) (note 1) symbol address after reset s3c 0362 16 0100000 16 s4c 0366 16 0100000 16 b7 b6 b5 b4 b3 b2 b1 b0 description smi5 smi1 smi0 smi3 smi6 smi7 internal synchronous clock select bit transfer direction select bit s i/oi port select bit s out i initial value set bit 0 0 : selecting f 1sio or f 2sio 0 1 : selecting f 8sio 1 0 : selecting f 32sio 1 1 : must not be set. b1 b0 0 : external clock 1 : internal clock effective when smi3 = 0 0 : l output 1 : h output 0 : input/output port 1 : s out i output, clki function bit name bit symbol synchronous clock select bit 0 : lsb first 1 : msb first smi2 s out i output disable bit 0 : s out i output 1 : s out i output disable (high impedance) note 1: make sure this register is written to by the next instruction after setting the prcr register's prc2 bit to 1 (write enable). note 2: set the smi3 bit to 1 (s out i output, clki function). note 3: set the smi3 bit to 1 and the corresponding port direction bit to 0 (input mode). note 4: effective when smi3 bit = 1. clk polarity select bit smi4 0 : transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : transmit data is output at rising edge of transfer clock and receive data is input at falling edge rw rw rw rw rw rw rw rw rw wo rw rw (note 4) (note 2) (note 3) note 1: write to this register while serial i/o is neither transmitting nor receiving. note 2: use mov instruction to write to this register. figure 1.21.2. s3c and s4c registers, s3brg and s4brg registers, and s3trr and s4trr registers
186 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. si/o3, si/o4 item specification transfer data format ? transfer data length: 8 bits transfer clock ? sic (i=3, 4) registers smi6 bit = 1 (internal clock) : fj/ 2(n+1) fj = f 1sio , f 8sio , f 32sio . n=setting value of sibrg register 00 16 to ff 16 . ? smi6 bit = 0 (external clock) : input from clki pin (note 1) transmission/reception ? before transmission/reception can start, the following requirements must be met start condition write transmit data to the sitrr register (notes 2, 3) ? when sic register's smi4 bit = 0 the rising edge of the last transfer clock pulse (note 4) ? when smi4 = 1 the falling edge of the last transfer clock pulse (note 4) clki pin fucntion i/o port, transfer clock input, transfer clock output s out i pin function i/o port, transmit data output, high-impedance sini pin function i/o port, receive data input select function ? lsb first or msb first selection whether to start sending/receiving data beginning with bit 0 or beginning with bit 7 can be selected ? function for setting an s out i initial value set function when the sic register's smi6 bit = 0 (external clock), the s out i pin output level while not tranmitting can be selected. ? clk polarity selection whether transmit data is output/input timing at the rising edge or falling edge of transfer clock can be selected. note 1: to set the sic registers smi6 bit to 0 (external clock), follow the procedure described below. ? if the sic registers smi4 bit = 0, write transmit data to the sitrr register while input on the clki pin is high. the same applies when rewriting the sic registers smi7 bit. ? if the smi4 bit = 1, write transmit data to the sitrr register while input on the clki pin is low. the same applies when rewriting the smi7 bit. ? because shift operation continues as long as the transfer clock is supplied to the si/oi circuit, stop the transfer clock after supplying eight pulses. if the smi6 bit = 1 (internal clock), the transfer clock automatically stops. note 2: unlike uart0 to uart2, si/oi (i = 3 to 4) is not separated between the transfer register and buffer. there- fore, do not write the next transmit data to the sitrr register during transmission. note 3: when the sic registers smi6 bit = 1 (internal clock), s outi retains the last data for a 1/2 transfer clock period after completion of transfer and, thereafter, goes to a high-impedance state. however, if transmit data is written to the sitrr register during this period, s outi immediately goes to a high-impedance state, with the data hold time thereby reduced. note 4: when the sic registers smi6 bit = 1 (internal clock), the transfer clock stops in the high state if the smi4 bit = 0, or stops in the low state if the smi4 bit = 1. table 1.21.1. si/o3 and si/o4 specifications interrupt request generation timing
187 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. si/o3, si/o4 (a) si/oi operation timing figure 1.21.3 shows the si/oi operation timing d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 i= 3, 4 1.5 cycle (max) si/oi internal clock clki output signal written to the sitrr register s out i output s in i input siic register ir bit (note 2) note 1: this diagram applies to the case where the sic register bits are set as follows: smi2=0 (s out i output), smi3=1 (s out i output, clki function), smi4=0 (transmit data output at the falling edge and receive data input at the rising edge of the transfer clock), smi5=0 (lsb first) and smi6=1 (internal clock) note 2: when the smi6 bit = 1 (internal clock), the s out i pin is placed in the high-impedance state after the transfer finishes. note 3: if the smi6 bit=0 (internal clock), the serial i/o starts sending or receiving data a maximum of 1.5 transfer clock cycles after writing to the sitrr register. "h" "l" "h" "l" "h" "l" "h" "l" "h" "l" "1" "0" (note 3) figure 1.21.3. si/oi operation timing (b) clk polarity selection the sic register's smi4 bit allows selection of the polarity of the transfer clock. figure 1.21.4 shows the polarity of the transfer clock. figure 1.21.4. polarity of transfer clock (2) when sic register's smi4 bit = 1 (note 3) d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 0 s ini s outi clk i (1) when sic register's smi4 bit = 0 note 1: this diagram applies to the case where the sic register bits are set as follows: smi5=0 (lsb first) and smi6=1 (internal clock) note 2: when the smi6 bit=1 (internal clock), a high level is output from the clki pin if not transferring data. note 3: when the smi6 bit=1 (internal clock), a low level is output from the clki pin if not transferring data. d 1 d 2 d 3 d 4 d 5 d 6 d 7 d0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 s ini s outi clk i (note 2) i=3 and 4
188 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. si/o3, si/o4 (c) functions for setting an s out i initial value if the sic registers smi6 bit = 0 (external clock), the s outi pin output can be fixed high or low when not transferring. figure 1.21.5 shows the timing chart for setting an s outi initial value and how to set it. figure 1.21.5. s out i s initial value setting setting of the initial value of s out i output and starting of transmission/ reception set the smi3 bit to 0 (s out i pin functions as an i/o port) write to the sitrr register serial transmit/reception starts set the smi7 bit to 1 (s out i initial value = h) set the smi3 bit to 1 (s out i pin functions as s out i output) h level is output from the s out i pin signal written to sitrr register s out i (internal) smi7 bit s out i pin output smi3 bit setting the s out i initial value to h port selection switching (i/o port s out i) d0 (i = 3, 4) initial value = h (note 3) port output d0 (example) when h selected for s out i initial value (note 1) note 1: this diagram applies to the case where the sic register bits are set as follows: smi2=0 (s out i output), smi5=0 (lsb first) and smi6=0 (external clock) note 2: s out i can only be initialized when input on the clki pin is in the high state if the sic registers smi4 bit = 0 (transmit data output at the falling edge of the transfer clock) or in the low state if the smi4 bit = 1 (transmit data output at the rising edge of the transfer clock). note 3: if the smi6 bit = 1 (internal clock) or if the smi2 bit = 1 (s out output disabled), this output goes to the high-impedance state. (note 2)
a-d converter 189 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. item performance method of a-d conversion successive approximation (capacitive coupling amplifier) analog input voltage (note 1) 0v to av cc (v cc1 ) operating clock ad (note 2) f ad /divide-by-2 of f ad /divide-by-3 of f ad /divide-by-4 of f ad /divide-by-6 of f ad /divide-by-12 of f ad resolution 8-bit or 10-bit (selectable) integral nonlinearity error when av cc = v ref = 5v ? with 8-bit resolution: 2lsb ? with 10-bit resolution - an 0 to an 7 input : 3lsb - an 00 to an0 7 input and an 20 to an 27 input : 7lsb - anex0 and anex1 input (including mode in which external operation amp is connected) : 7lsb when av cc = v ref = 3.3v ? with 8-bit resolution: 2lsb ? with 10-bit resolution - an 0 to an 7 input : 5lsb - an 00 to an0 7 input and an 20 to an 27 input : 7lsb - anex0 and anex1 input (including mode in which external operation amp is connected) : 7lsb operating modes one-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, and repeat sweep mode 1 analog input pins 8 pins (an 0 to an 7 ) + 2 pins (anex0 and anex1) + 8 pins (an 00 to an 07 ) + 8 pins (an 20 to an 27 ) a-d conversion start condition ? software trigger the adcon0 register's adst bit is set to 1 (a-d conversion starts) ? external trigger (retriggerable) ___________ input on the ad trg pin changes state from high to low after the adst bit is set to 1 (a-d conversion starts) conversion speed per pin ? without sample and hold function 8-bit resolution: 49 ad cycles , 10-bit resolution: 59 ad cycles ? with sample and hold function 8-bit resolution: 28 ad cycles , 10-bit resolution: 33 ad cycles a-d converter the microcomputer contains one a-d converter circuit based on 10-bit successive approximation method configured with a capacitive-coupling amplifier. the analog inputs share the pins with p10 0 to p10 7 , p9 5 , ___________ p9 6 , p0 0 to p0 7 , and p2 0 to p2 7 . similarly, ad trg input shares the pin with p9 7 . therefore, when using these inputs, make sure the corresponding port direction bits are set to 0 (= input mode). when not using the a-d converter, set the vcut bit to 0 (= vref unconnected), so that no current will flow from the v ref pin into the resistor ladder, helping to reduce the power consumption of the chip. the a-d conversion result is stored in the adi register bits for ani, an0i, and an2i pins (i = 0 to 7). table 1.22.1 shows the performance of the a-d converter. figure 1.22.1 shows the block diagram of the a-d converter, and figures 1.22.2 and 1.22.3 show the a-d converter-related registers. table 1.22.1. performance of a-d converter note 1: does not depend on use of sample and hold function. note 2: the f ad frequency must be 10 mhz or less. without sample-and-hold function, limit the f ad frequency to 250kh z or less. with the sample and hold function, limit the f ad frequency to 1mh z or less. note 3: if v cc2 < v cc1 , do not use an 00 to an 07 and an 20 to an 27 as analog input pins.
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r a-d converter 190 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.22.1. a-d converter block diagram anex 0 anex 1 opa0=1 opa1=1 pm01 to pm00=00 2 adgsel1 to adgsel0=10 2 opa1 to opa0=11 2 adgsel1 to adgsel0=00 2 opa1 to opa0=11 2 =000 2 =001 2 =010 2 =011 2 =100 2 =101 2 =110 2 =111 2 an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 an 00 an 01 an 02 an 03 an 04 an 05 an 06 an 07 v ref v in ch2 to ch0 pm00 pm01 decoder for channel selection ad register 0(16) data bus low-order v ref av ss vcut=0 vcut=1 data bus high-order opa1=1 port p10 group port p0 group pm01 to pm00=00 2 adgsel1 to adgsel0=10 2 opa1 to opa0=00 2 adgsel1 to adgsel0=00 2 opa1 to opa0=00 2 opa1 to opa0 =01 2 an 20 an 21 an 22 an 23 an 24 an 25 an 26 an 27 pm01 to pm00=00 2 adgsel1 to adgsel0=11 2 opa1 to opa0=11 2 pm01 to pm00=00 2 adgsel1 to adgsel0=11 2 opa1 to opa0=00 2 f ad cks0=1 cks0=0 cks1=1 cks1=0 1/3 cks2=0 cks2=1 1/2 1/2 ? ad a-d conversion rate selection (03c1 16 to 03c0 16 ) (03c3 16 to 03c2 16 ) (03c5 16 to 03c4 16 ) (03c7 16 to 03c6 16 ) (03c9 16 to 03c8 16 ) (03cb 16 to 03ca 16 ) (03cd 16 to 03cc 16 ) (03cf 16 to 03ce 16 ) resistor ladder successive conversion register adcon0 register (address 03d6 16 ) adcon1 register (address 03d7 16 ) comparator addresses decoder for a-d register ad register 1(16) ad register 2(16) ad register 3(16) ad register 4(16) ad register 5(16) ad register 6(16) ad register 7(16) adcon2 register (address 03d4 16 ) port p2 group ad trg trg=0 trg=1 a-d trigger software trigger =000 2 =001 2 =010 2 =011 2 =100 2 =101 2 =110 2 =111 2 =000 2 =001 2 =010 2 =011 2 =100 2 =101 2 =110 2 =111 2 ch2 to ch0 ch2 to ch0 (note) note: port p0 group (an 00 to an 07 ) can be used as analog input pins even when pm01 to pm00 bits are set to 01 2 (memory expansion mode) and pm05 to pm04 bits are set to 11 2 (multiplex bus allocated to the entire cs space).
a-d converter 191 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.22.2. adcon0 to adcon1 registers a-d control register 0 (note) symbol address after reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 0 0 : one-shot mode 0 1 : repeat mode 1 0 : single sweep mode 1 1 : repeat sweep mode 0 or repeat sweep mode 1 md0 md1 trigger select bit 0 : software trigger 1 : ad trg trigger trg adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 s ee note 3 for the adcon2 register cks0 rw a-d control register 1 (note 1) symbol address after reset adcon1 03d7 16 00 16 bit name functionbit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut opa0 vref connect bit (note 2) opa1 a-d operation mode select bit 1 0 : any mode other than repeat sweep mode 1 1 : repeat sweep mode 1 0 : vref not connected 1 : vref connected external op-amp connection mode bit b4 b3 note: if the adcon0 register is rewritten during a-d conversion, the conversion result will be indeterminate. frequency select bit 1 cks1 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw function varies with each operation mode function varies with each operation mode see note 3 for the adcon2 register note 1: if the adcon1 register is rewritten during a-d conversion, the conversion result will be indeterminate. note 2: if the vcut bit is reset from 0 (vref unconnected) to 1 (vref connected), wait for 1 s or more before starting a-d conversion. function varies with each operation mode
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r a-d converter 192 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. a-d control register 2 (note 1) symbol address a fter reset adcon2 03d4 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 a-d conversion method select bit 0 : without sample and hold 1 : with sample and hold bit symbol bit name function rw smp reserved bit must always be set to 0 0 note 1: if the adcon2 register is rewritten during a-d conversion, the conversion result will be indeterminate. note 2: if v cc2 < v cc1 , do not use an 00 to an 07 and an 20 to an 27 as analog input pins. note 3: the ? ad frequency must be 10 mhz or less. the selected ? ad frequency is determined by a combination of the adcon0 register's cks0 bit, adcon1 register's cks1 bit, and adcon2 register's cks2 bit. a-d input group select bit 0 0 : port p10 group is selected 0 1 : must not be set 1 0 : port p0 group is selected (note 3) 1 1 : port p2 group is selected b2 b1 frequency select bit 2 (note 3) cks2 adgsel0 adgsel1 rw rw rw rw rw a-d register i (i=0 to 7) symbol address a fter reset ad0 03c1 16 to 03c0 16 indeterminate ad1 03c3 16 to 03c2 16 indeterminate ad2 03c5 16 to 03c4 16 indeterminate ad3 03c7 16 to 03c6 16 indeterminate ad4 03c9 16 to 03c8 16 indeterminate ad5 03cb 16 to 03ca 16 indeterminate ad6 03cd 16 to 03cc 16 indeterminate ad7 03cf 16 to 03ce 16 indeterminate eight low-order bits of a-d conversion result function (b15) b7b7 b0 b0 (b8) when the adcon1 register's bits bit is 1 (10-bit mode) nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be 0. when read, the content is indeterminate rw ro ro (b3) nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be 0. (b7-b5) 0: selects f ad , f ad divided by 2, or f ad divided by 4. 1: selects f ad divided by 3, f ad divided by 6, or f ad divided by 12. cks0 cks1 cks2 ? ad 000 001 010 100 101 110 111 divide-by-4 of f ad divide-by-2 of f ad f ad ddivide-by-12 of f ad 011 divide-by-6 of f ad divide-by-3 of f ad two high-order bits of a-d conversion result when the adcon1 register's bits bit is 0 (8-bit mode) a-d conversion result figure 1.22.3. adcon2 register, and ad0 to ad7 registers
a-d converter 193 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. (1) one-shot mode in this mode, the input voltage on one selected pin is a-d converted once. table 1.22.2 shows the specifications of one-shot mode. figure 1.22.4 shows the adcon0 to adcon1 registers in one-shot mode. table 1.22.2. one-shot mode specifications item specification function the input voltage on one pin selected by the adcon0 register's ch2 to ch0 bits and adcon2 register's adgsel1 to adgsel0 bits or the adcon1 register's opa1 to opa0 bits is a-d converted once. a-d conversion start condition ? when the adcon0 register's trg bit is 0 (software trigger) the adcon0 register's adst bit is set to 1 (a-d conversion starts) ___________ ? when the trg bit is 1 (ad trg trigger) ___________ input on the ad trg pin changes state from high to low after the adst bit is set to 1 (a-d conversion starts) a-d conversion stop condtision ? completion of a-d conversion (if a software trigger is selected, the adst bit is cleared to 0 (a-d conversion halted).) ? set the adst bit to 0 interrupt request generation timing completion of a-d conversion analog input pin (note) select one pin from an 0 to an 7 , an 00 to an 07 , an 20 to an 27 , anex0 to anex1 reading of result of a-d converter read one of the ad0 to ad7 registers that corresponds to the selected pin note: if v cc2 < v cc1 , do not use an 00 Can 07 and an 20 Can 27 as analog input pins.
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r a-d converter 194 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. a-d control register 0 (note 1) symbol address a fter reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 md0 md1 trigger select bit 0 : software trigger 1 : ad trg trigger trg adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 cks0 rw 00 a-d control register 1 (note) symbol address a fter reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut opa0 vref connect bit (note 2) opa1 a-d operation mode select bit 1 set to 0 when one-shot mode is selected 1 : vref connected external op-amp connection mode bit 0 0 : anex0 and anex1 are not used 0 1 : anex0 input is a-d converted 1 0 : anex1 input is a-d converted 1 1 : external op-amp connection mode rw invalid in one-shot mode 0 0 0 0 : an 0 is selected 0 0 1 : an 1 is selected 0 1 0 : an 2 is selected 0 1 1 : an 3 is selected 1 0 0 : an 4 is selected 1 0 1 : an 5 is selected 1 1 0 : an 6 is selected (note 2) 1 1 1 : an 7 is selected (note 3) b2 b1 b0 0 0 : one-shot mode (note 3) b4 b3 ch0 b7 b6 1 frequency select bit1 cks1 note 1: if the adcon0 register is rewritten during a-d conversion, the conversion result will be indeterminate. note 2: an 00 to an 07 , and an 20 to an 27 can be used in the same way as an 0 to an 7 . use the adcon2 registers adgsel1 to adgsel0 bits to select the desired pin. however, if v cc2 < v cc1 , do not use an 00 to an 07 and an 20 to an 27 as analog input pins. note 3: after rewriting the md1 to md0 bits, set the ch2 to ch0 bits over again using another instruction. rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw see note 3 for the adcon2 register see note 3 for the adcon2 register note 1: if the adcon1 register is rewritten during a-d conversion, the conversion result will be indeterminate. note 2: if the vcut bit is reset from 0 (vref unconnected) to 1 (vref connected), wait for 1 s or more before starting a-d conversion. figure 1.22.4. adcon0 register and adcon1 register (one-shot mode)
a-d converter 195 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. (2) repeat mode i n this mode, the input voltage on one selected pin is a-d converted repeatedly. table 1.22.3 shows the specifications of repeat mode. figure 1.22.5 shows the adcon0 to adcon1 registers in repeat mode. item specification function the input voltage on one pin selected by the adcon0 register's ch2 to ch0 bits and adcon2 register's adgsel1 to adgsel0 bits or the adcon1 register's opa1 to opa0 bits is a-d converted repeatdly. a-d conversion start condition ? when the adcon0 register's trg bit is 0 (software trigger) the adcon0 register's adst bit is set to 1 (a-d conversion starts) ___________ ? when the trg bit is 1 (ad trg trigger) ___________ input on the ad trg pin changes state from high to low after the adst bit is set to 1 (a-d conversion starts) a-d conversion stop condtision set the adst bit to 0 (a-d conversion halted) interrupt request generation timing none generated analog input pin (note) select one pin from an 0 to an 7 , an 00 to an 07 , an 20 to an 27 , anex0 to anex1 reading of result of a-d converter read one of the ad0 to ad7 registers that corresponds to the selected pin note: if v cc2 < v cc1 , do not use an 00 Can 07 and an 20 Can 27 as analog input pins. table 1.22.3. repeat mode specifications
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r a-d converter 196 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. a-d control register 0 (note 1) symbol address after reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 md0 md1 trigger select bit 0 : software trigger 1 : ad trg trigger trg adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 cks0 rw a-d control register 1 (note) symbol address a fter reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut opa0 vref connect bit (note 2) opa1 a-d operation mode select bit 1 1 : vref connected external op-amp connection mode bit 01 invalid in repeat mode 0 0 0 0 : an 0 is selected 0 0 1 : an 1 is selected 0 1 0 : an 2 is selected 0 1 1 : an 3 is selected 1 0 0 : an 4 is selected 1 0 1 : an 5 is selected 1 1 0 : an 6 is selected (note 2) 1 1 1 : an 7 is selected (note 3) b2 b1 b0 0 1 : repeat mode (note 3) b4 b3 0 0 : anex0 and anex1 are not used 0 1 : anex0 input is a-d converted 1 0 : anex1 input is a-d converted 1 1 : external op-amp connection mode b7 b6 1 frequency select bit 1 cks1 set to 0 when this mode is selected rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw see note 3 for the adcon2 register note 1: if the adcon0 register is rewritten during a-d conversion, the conversion result will be indeterminate. note 2: an 00 to an 07 , and an 20 to an 27 can be used in the same way as an 0 to an 7 . use the adcon2 registers adgsel1 to adgsel0 bits to select the desired pin. however, if v cc2 < v cc1 , do not use an 00 to an 07 and an 20 to an 27 as analog input pins. note 3: after rewriting the md1 to md0 bits, set the ch2 to ch0 bits over again using another instruction. note 1: if the adcon1 register is rewritten during a-d conversion, the conversion result will be indeterminate. note 2: if the vcut bit is reset from 0 (vref unconnected) to 1 (vref connected), wait for 1 s or more before starting a-d conversion. see note 3 for the adcon2 register figure 1.22.5. adcon0 register and adcon1 register (repeat mode)
a-d converter 197 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. (3) single sweep mode i n this mode, the input voltages on selected pins are a-d converted, one pin at a time. table 1.22.4 shows the specifications of single sweep mode. figure 1.22.6 shows the adcon0 to adcon1 registers in single sweep mode. item specification function the input voltages on pins selected by the adcon1 register's scan1 to scan0 bits and adcon2 register's adgsel1 to adgsel0 bits are a-d con- verted, one pin at a time. a-d conversion start condition ? when the adcon0 register's trg bit is 0 (software trigger) the adcon0 register's adst bit is set to 1 (a-d conversion starts) ___________ ? when the trg bit is 1 (ad trg trigger) ___________ input on the ad trg pin changes state from high to low after the adst bit is set to 1 (a-d conversion starts) a-d conversion stop condtision ? completion of a-d conversion (if a software trigger is selected, the adst bit is cleared to 0 (a-d conversion halted).) ? set the adst bit to 0 interrupt request generation timing completion of a-d conversion analog input pin select from an 0 to an 1 (2 pins), an 0 to an 3 (4 pins), an 0 to an 5 (6 pins), an 0 to an 7 (8 pins) (note) reading of result of a-d converter read one of the ad0 to ad7 registers that corresponds to the selected pin note: an 00 to an 07 , and an 20 to an 27 can be used in the same way as an 0 to an 7 . however, if v cc2 < v cc1 , do not use an 00 Can 07 and an 20 Can 27 as analog input pins. table 1.22.4. single sweep mode specifications
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r a-d converter 198 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. a-d control register 0 (note) symbol address a fter reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 1 0 : single sweep mode md0 md1 trigger select bit 0 : software trigger 1 : ad trg trigger trg adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 cks0 rw 1 0 invalid in single sweep mode b4 b3 rw rw rw rw rw rw rw rw a-d control register 1 (note 1) symbol address after reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut opa0 vref connect bit (note 3) opa1 a-d operation mode select bit 1 1 : vref connected external op-amp connection mode bit 0 when single sweep mode is selected 0 0 : an 0 to an 1 (2 pins) 0 1 : an 0 to an 3 (4 pins) 1 0 : an 0 to an 5 (6 pins) 1 1 : an 0 to an 7 (8 pins) (note 2) b1 b0 0 0 : anex0 and anex1 are not used 0 1 : must not be set 1 0 : must not be set 1 1 : external op-amp connection mode b7 b6 1 frequency select bit 1 cks1 set to 0 when single sweep mode is selected rw rw rw rw rw rw rw rw rw see note 3 for the adcon2 register note: if the adcon0 register is rewritten during a-d conversion, the conversion result will be indeterminate. note 1: if the adcon1 register is rewritten during a-d conversion, the conversion result will be indeterminate. note 2: an 00 to an 07 , and an 20 to an 27 can be used in the same way as an 0 to an 7 . use the adcon2 registers adgsel1 to adgsel0 bits to select the desired pin. however, if v cc2 < v cc1 , do not use an 00 to an 07 and an 20 to an 27 as analog input pins. note 3: if the vcut bit is reset from 0 (vref unconnected) to 1 (vref connected), wait for 1 s or more before starting a-d conversion. see note 3 for the adcon2 register figure 1.22.6. adcon0 register and adcon1 register (single sweep mode)
a-d converter 199 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. (4) repeat sweep mode 0 in this mode, the input voltages on selected pins are a-d converted repeatedly. table 1.22.5 shows the specifications of repeat sweep mode 0. figure 1.22.7 shows the adcon0 to adcon1 registers in repeat sweep mode 0. item specification function the input voltages on pins selected by the adcon1 register's scan1 to scan0 bits and adcon2 register's adgsel1 to adgsel0 bits are a-d con- verted repeatdly. a-d conversion start condition ? when the adcon0 register's trg bit is 0 (software trigger) the adcon0 register's adst bit is set to 1 (a-d conversion starts) ___________ ? when the trg bit is 1 (ad trg trigger) ___________ input on the ad trg pin changes state from high to low after the adst bit is set to 1 (a-d conversion starts) a-d conversion stop condtision set the adst bit to 0 (a-d conversion halted) interrupt request generation timing none generated analog input pin select from an 0 to an 1 (2 pins), an 0 to an 3 (4 pins), an 0 to an 5 (6 pins), an 0 to an 7 (8 pins) (note) reading of result of a-d converter read one of the ad0 to ad7 registers that corresponds to the selected pin note: an 00 to an 07 , and an 20 to an 27 can be used in the same way as an 0 to an 7 . however, if v cc2 < v cc1 , do not use an 00 Can 07 and an 20 Can 27 as analog input pins. table 1.22.5. repeat sweep mode 0 specifications
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r a-d converter 200 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. a-d control register 0 (note) symbol address a fter reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 1 1 : repeat sweep mode 0 or repeat sweep mode 1 md0 md1 trigger select bit 0 : software trigger 1 : ad trg trigger trg adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 cks0 rw a-d control register 1 (note 1) symbol address a fter reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut opa0 vref connect bit (note 3) opa1 a-d operation mode select bit 1 1 : vref connected external op-amp connection mode bit 1 1 invalid in repeat sweep mode 0 0 b4 b3 when repeat sweep mode 0 is selected 0 0 : an 0 , an 1 (2 pins) 0 1 : an 0 to an 3 (4 pins) 1 0 : an 0 to an 5 (6 pins) 1 1 : an 0 to an 7 (8 pins) (note 2) b1 b0 0 0 : anex0 and anex1 are not used 0 1 : must not be set 1 0 : must not be set 1 1 : external op-amp connection mode b7 b6 1 frequency select bit 1 cks1 set to 0 when repeat sweep mode 0 is selected rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw see note 3 for the adcon2 register note: if the adcon0 register is rewritten during a-d conversion, the conversion result will be indeterminate. note 1: if the adcon1 register is rewritten during a-d conversion, the conversion result will be indeterminate. note 2: an 00 to an 07 , and an 20 to an 27 can be used in the same way as an 0 to an 7 . use the adcon2 registers adgsel1 to adgsel0 bits to select the desired pin. however, if v cc2 < v cc1 , do not use an 00 to an 07 and an 20 to an 27 as analog input pins. note 3: if the vcut bit is reset from 0 (vref unconnected) to 1 (vref connected), wait for 1 s or more before starting a-d conversion. see note 3 for the adcon2 register figure 1.22.7. adcon0 register and adcon1 registers (repeat sweep mode 0)
a-d converter 201 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. (5) repeat sweep mode 1 in this mode, the input voltages on all pins are a-d converted repeatedly, with priority given to the se- lected pins. table 1.22.6 shows the specifications of repeat sweep mode 1. figure 1.22.8 shows the adcon0 to adcon1 registers in repeat sweep mode 1. table 1.22.6. repeat sweep mode 1 specifications item specification function the input voltages on all pins selected by the adcon2 register's adgsel1 to adgsel0 bits are a-d converted repeatdly, with priority given to pins se- lected by the adcon1 register's scan1 to scan0 bits and adgsel1 to adgsel0 bits. example : if an 0 selected, input voltages are a-d converted in order of an 0 an 1 an 0 an 2 an 0 an 3 , and so on. a-d conversion start condition ? when the adcon0 register's trg bit is 0 (software trigger) the adcon0 register's adst bit is set to 1 (a-d conversion starts) ___________ ? when the trg bit is 1 (ad trg trigger) ___________ input on the ad trg pin changes state from high to low after the adst bit is set to 1 (a-d conversion starts) a-d conversion stop condtision set the adst bit to 0 (a-d conversion halted) interrupt request generation timing none generated select from an 0 (1 pins), an 0 to an 1 (2 pins), an 0 to an 2 (3 pins), an 0 to an 3 (4 pins) (note) reading of result of a-d converter read one of the ad0 to ad7 registers that corresponds to the selected pin note: an 00 to an 07 , and an 20 to an 27 can be used in the same way as an 0 to an 7 . however, if v cc2 < v cc1 , do not use an 00 Can 07 and an 20 Can 27 as analog input pins. analog input pins to be given priority when a-d converted
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r a-d converter 202 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. a-d control register 0 (note) symbol address a fter reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 1 1 : repeat sweep mode 0 or repeat sweep mode 1 md0 md1 trigger select bit 0 : software trigger 1 : ad trg trigger trg adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 cks0 rw a-d control register 1 (note 1) symbol address a fter reset adcon1 03d7 16 00 16 bit name functionbit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut opa0 vref connect bit (note 3) opa1 a-d operation mode select bit 1 1 : vref connected external op-amp connection mode bit 1 1 invalid in repeat sweep mode 1 1 b4 b3 when repeat sweep mode 1 is selected 0 0 : an 0 (1 pin) 0 1 : an 0 , an 1 (2 pins) 1 0 : an 0 to an 2 (3 pins) 1 1 : an 0 to an 3 (4 pins) ( note 2) b1 b0 0 0 : anex0 and anex1 are not used 0 1 : must not be set 1 0 : must not be set 1 1 : external op-amp connection mode b7 b6 1 frequency select bit 1 cks1 set to 1 when repeat sweep mode 1 is selected rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw see note 3 for the adcon2 register note: if the adcon0 register is rewritten during a-d conversion, the conversion result will be indeterminate. note 1: if the adcon1 register is rewritten during a-d conversion, the conversion result will be indeterminate. note 2: an 00 to an 07 , and an 20 to an 27 can be used in the same way as an 0 to an 7 . use the adcon2 registers adgsel1 to adgsel0 bits to select the desired pin. however, if v cc2 < v cc1 , do not use an 00 to an 07 and an 20 to an 27 as analog input pins. note 3: if the vcut bit is reset from 0 (vref unconnected) to 1 (vref connected), wait for 1 s or more before starting a-d conversion. see note 3 for the adcon2 register figure 1.22.8. adcon0 register and adcon1 register (repeat sweep mode 1)
a-d converter 203 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. (a) resolution select function the desired resolution can be selected using the adcon1 registers bits bit. if the bits bit is set to 1 (10-bit conversion accuracy), the a-d conversion result is stored in the adi register (i = 0 to 7)'s bit 0 to bit 9. if the bits bit is set to 0 (8-bit conversion accuracy), the a-d conversion result is stored in the adi register's bit 0 to bit 7. (b) sample and hold if the adcon2 registers smp bit is set to 1 (with sample-and-hold), the conversion speed per pin is increased to 28 ?ad cycles for 8-bit resolution or 33 ?ad cycles for 10-bit resolution. sample-and-hold is effective in all operation modes. select whether or not to use the sample-and-hold function before starting a-d conversion. (c) extended analog input pins in one-shot and repeat modes, the anex0 and anex1 pins can be used as analog input pins. use the adcon1 registers opa1 to opa0 bits to select whether or not use anex0 and anex1. the a-d conversion results of anex0 and anex1 inputs are stored in the ad0 and ad1 registers, respectively. (d) external operation amp connection mode multiple analog inputs can be amplified using a single external op-amp via the anxe0 and anex1 pins. set the adcon1 registers opa1 opa0 bits to 11 2 (external op-amp connection mode). the inputs from ani (i = 0 to 7) (note 1) are output from the anex0 pin. amplify this output with an external op-amp before sending it back to the anex1 pin. the a-d conversion result is stored in the corresponding adi register. the a-d conversion speed depends on the response characteristics of the external op-amp. note that the anxe0 and anex1 pins cannot be directly connected to each other. figure 1.22.9 is an example of how to connect the pins in external operation amp. note: an 0i and an 2i can be used the same as an i . however, if v cc2 < v cc1 , do not use an 0i and an 2i as analog input pins. adcon2 register's adgsel1 to adgsel0 bits=00 2 successive conversion register comparator external op- amp an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 anex0 anex1 an 00 an 01 an 02 an 03 an 04 an 05 an 06 an 07 adgsel1 to adgsel0 bits=10 2 an 20 an 21 an 22 an 23 an 24 an 25 an 26 an 27 adgsel1 to adgsel0 bits=11 2 resistor ladder microcomputer figure 1.22.9. external op-amp connection
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r a-d converter 204 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. (e) current consumption reducing function when not using the a-d converter, its resistor ladder and reference voltage input pin (v ref ) can be separated using the adcon1 registers vcut bit. when separated, no current will flow from the v ref pin into the resistor ladder, helping to reduce the power consumption of the chip. to use the a-d converter, set the vcut bit to 1 (v ref connected) and then set the adcon0 registers adst bit to 1 (a-d conversion start). the vcut and adst bits cannot be set to 1 at the same time. nor can the vcut bit be set to 0 (v ref unconnected) during a-d conversion. note that this does not affect v ref for the d-a converter (irrelevant). (f) analog input pin and external sensor equivalent circuit example figure 1.22.10 shows analog input pin and external sensor equivalent circuit example. figure 1.22.10. analog input pin and external sensor equivalent circuit r 0 r (7.8k ? ) c (3.0pf) v in v c sampling time 3 f ad sample-and-hold function enabled: 2 f ad sample-and-hold function disabled: microcomputer sensor equivalent circuit
a-d converter 205 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. microcomputer note 1: c1 0.47 f, c2 0.47 f, c3 100pf, c4 0.1 f, c5 0.1 f (reference) note 2: use thick and shortest possible wiring to connect capacitors. v cc1 v ss av cc av ss v ref ani c4 c1 c2 c3 v cc2 v ss c5 ani: ani, an 0 i, and an 2 i (i=0 to 7) (g) caution of using a-d converter (1) make sure the port direction bits for those pins that are used as analog inputs are set to 0 (input mode). also, if the adcon0 registers tgr bit = 1 (external trigger), make sure the port direction bit ___________ for the ad trg pin is set to 0 (input mode). (2) when using key input interrupts, do not use any of the four an 4 to an 7 pins as analog inputs. (a key input interrupt request is generated when the a-d input voltage goes low.) (3) to prevent noise-induced device malfunction or latchup, as well as to reduce conversion errors, insert capacitors between the av cc , v ref , and analog input pins (ani (i=0 to 7), an 0 i, and an 2 i) each and the av ss pin. similarly, insert a capacitor between the v cc pin and the v ss pin. figure 1.22.11 is an example connection of each pin. (4) if v cc2 < v cc1 , do not use an 00 to an 07 and an 20 to an 27 as analog input pins. (5) if the cpu reads the adi register (i = 0 to 7) at the same time the conversion result is stored in the adi register after completion of a-d conversion, an incorrect value may be stored in the adi register. this problem occurs when a divide-by-n clock derived from the main clock or a subclock is selected for cpu clock. ? when operating in one-shot or single-sweep mode check to see that a-d conversion is completed before reading the target adi register. (check the ir bit in the adic register to see if a-d conversion is completed.) ? when operating in repeat mode or repeat sweep mode 0 or 1 use the main clock for cpu clock directly without dividing it. (6) if a-d conversion is forcibly terminated while in progress by setting the adcon0 registers adst bit to 0 (a-d conversion halted), the conversion result of the a-d converter is indeterminate. the con- tents of adi registers irrelevant to a-d conversion may also become indeterminate. if while a-d con- version is underway the adst bit is cleared to 0 in a program, ignore the values of all adi registers. figure 1.22.11. v cc , v ss , av cc , av ss , v ref and ani connection
d-a converter 206 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. d-a converter this is an 8-bit, r-2r type d-a converter. these are two independent d-a converters. d-a conversion is performed by writing to the dai register (i = 0 to 1). to output the result of conversion, set the dacon registers daie bit to 1 (output enabled). before d-a conversion can be used, the correspond- ing port direction bit must be cleared to 0 (input mode). setting the daie bit to 1 removes a pull-up from the corresponding port. output analog voltage (v) is determined by a set value (n : decimal) in the dai register. v = v ref x n/ 256 (n = 0 to 255) v ref : reference voltage table 1.23.1 lists the performance of the d-a converter. figure 1.23.1 shows the block diagram of the d-a converter. figure 1.23.2 shows the d-a converter related registers. figure 1.23.3 shows the d-a converter equivalent circuit. item performance d-a conversion method r-2r method resolution 8 bits analog output pin 2 (da0 and da1) table 1.23.1. d-a converter performance aaaa da 0 aaaa da 1 data bus low-order da0 register r-2r resistor ladder da0e bit da1 register r-2r resistor ladder da1e bit figure 1.23.1. d-a converter block diagram
d-a converter 207 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.23.2. dacon register, da0 register, and da1 register d-ai register (note) (i= 0 to 1) symbol address a fter reset da0 03d8 16 indeterminate da1 03da 16 indeterminate wr b7 b0 function rw output value of d-a conversion d-a control register (note) symbol address a fter reset dacon 03dc 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 d-a0 output enable bit da0e bit symbol bit name function rw 0 : output disabled 1 : output enabled d-a1 output enable bit 0 : output disabled 1 : output enabled da1e nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be 0 rw rw rw (b7-b2) rw note: when not using the d-a converter, clear the daie bit (i = 0 to 1) to 0 (output disabled) to reduce the unnecessary current consumption in the chip and set the dai register to 00 16 to prevent current from flowing into the r-2r resistor ladder. note: when not using the d-a converter, clear the daie bit (i = 0 to 1) to 0 (output disabled) to reduce the unnecessary current consumption in the chip and set the dai register to 00 16 to prevent current from flowing into the r-2r resistor ladder. v ref av ss 2r r 2r r 2r r 2r r 2r r 2r r 2r r 2r 2r dai msb lsb daie bit 0 1 dai register note: the above diagram shows an instance in which the da0 register is assigned 2a 16 . 0 1 r figure 1.23.3. d-a converter equivalent circuit
crc calculation 208 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. crc calculation the cyclic redundancy check (crc) operation detects an error in data blocks. the microcomputer uses a generator polynomial of crc_ccitt (x 16 + x 12 + x 5 + 1) to generate crc code. the crc code consists of 16 bits which are generated for each data block in given length, separated in 8 bit units. after the initial value is set in the crcd register, the crc code is set in that register each time one byte of data is written to the crcin register. crc code generation for one-byte data is finished in two cycles. figure 1.24.1 shows the block diagram of the crc circuit. figure 1.24.2 shows the crc-related registers. figure 1.24.3 shows the calculation example using the crc operation. figure 1.24.2. crcd register and crcin register symbol address after reset crcd 03bd 16 to 03bc 16 indeterminate b7 b0 b7 b0 (b15) (b8) crc data register function setting range 0000 16 to ffff 16 symbo address after reset crcin 03be 16 indeterminate b7 b0 crc input register data input function 00 16 to ff 16 rw rw rw rw setting range when data is written to the crcin register after setting the initial value in the crcd register, the crc code can be read out from the crcd register. aaaaa eight low-order bits aaaaaaa eight high-order bits data bus high-order data bus low-order aaaaaaaaaaa aaaaaaaaaaa aaaaaa aaaaaa crcd register crcin register aaaaaaaaaaa a aaaaaaaaa a aaaaaaaaaaa crc code generating circuit x 16 + x 12 + x 5 + 1 figure 1.24.1. crc circuit block diagram
crc calculation 209 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. (2) write 0000 16 (initial value) b15 b0 crcd register 1 0001 0000 0010 0001 1000 0000 0000 0000 0000 0000 1000 1000 0001 0000 1 1000 0001 0000 1000 0 1000 1000 0001 0000 1 1001 0001 1000 1000 1000 1000 generator polynomial data crc code modulo-2 operation is operation that complies with the law given below. 0 + 0 = 0 0 + 1 = 1 1 + 0 = 1 1 + 1 = 0 -1 = 1 setup procedure and crc operation when generating crc code 80c4 16 (a) crc operation performed by the m16c crc code: remainder of a division in which the value written to the crcin register with its bit positions reversed is divided by the generator polynomial (1) reverse the bit positions of the value 80c4 16 bytewise in a program. (3) write 01 16 b0b7 b15 b0 crcin register crcd register 1189 16 two cycles later, the crc code for 80 16 , i.e., 9188 16 , has its bit positions reversed to become 1189 16 which is stored in the crcd register. (c) details of crc operation in the case of (3) above, the value written to the crcin register 01 16 (00000001 2 ) has its bit positions reversed to become 10000000 2 . the value 1000 0000 0000 0000 0000 0000 2 derived from that by adding 16 digits and the crcd registers initial value 0000 16 are added, the result of which is divided by the generator polynomial using modulo-2 arithmetic. the value 0001 0001 1000 1001 2 (1189 16 ) derived from the remainder 1001 0001 1000 1000 2 (9188 16 ) by reversing its bit positions may be read from the crcd register. if operation (4) above is performed subsequently, the value written to the crcin register 23 16 (00100011 2 ) has its bit positions reversed to become 11000100 2 . the value 1100 0100 0000 0000 0000 0000 2 derived from that by adding 16 digits and the remainder in (3) 1001 0001 1000 1000 2 which is left in the crcd register are added, the result of which is divided by the generator polynomial using modulo-2 arithmetic. the value 0000 1010 0100 0001 2 (0a41 16 ) derived from the remainder by reversing its bit positions may be read from the crcd register. (b) setting procedure generator polynomial: x 16 + x 12 + x 5 + 1 (1 0001 0000 0010 0001 2 ) 80 16 01 16 , c4 16 23 16 (4) write 23 16 b0b7 b15 b0 0a41 16 crcin register crcd register two cycles later, the crc code for 80c4 16 , i.e., 8250 16 , has its bit positions reversed to become 0a41 16 which is stored in the crcd register. figure 1.24.3. crc calculation
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r programmable i/o ports 210 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. programmable i/o ports the programmable input/output ports (hereafter referred to simply as i/o ports) consist of 87 lines p0 to p10 (except p8 5 ) for the 100-pin version, or 113 lines p0 to p14 (except p8 5 ) for the 128-pin version. each port can be set for input or output every line by using a direction register, and can also be chosen to be or not be pulled high every 4 lines. p8 5 is an input-only port and does not have a pull-up resistor. port p8 5 _______ ______ shares the pin with nmi, so that the nmi input level can be read from the p8 register p8_5 bit. figures 1.25.1 to 1.25.4 show the i/o ports. figure 1.25.5 shows the i/o pins. each pin functions as an i/o port, a peripheral function input/output, or a bus control pin. for details on how to set peripheral functions, refer to each functional description in this manual. if any pin is used as a peripheral function input or d-a converter output pin, set the direction bit for that pin to 0 (input mode). any pin used as an output pin for peripheral functions other than the d-a converter is directed for output no matter how the corresponding direction bit is set. when using any pin as a bus control pin, refer to bus control. p0 to p5, p12, and p13 are capable of v cc2 -level input/output; p6 to p11 and p14 are capable of v cc1 - level input/output. (1) port pi direction register (pdi register, i = 0 to 13) figure 1.25.6 shows the direction registers. this register selects whether the i/o port is to be used for input or output. the bits in this register corre- spond one for one to each port. during memory extension and microprocessor modes, the pdi registers for the pins functioning as bus _______ _______ _______ _________ ______ __________________ _________ _________ _________ control pins (a 0 to a 19 , d 0 to d 15 , cs0 to cs3, rd, wrl/wr, wrh/bhe, ale, rdy, hold, hlda, and bclk) cannot be modified. no direction register bit for p8 5 is available. (2) port pi register (pi register, i = 0 to 13) figure 1.25.7 and 1.25.8 show the pi registers. data input/output to and from external devices are accomplished by reading and writing to the pi register. the pi register consists of a port latch to hold the input/output data and a circuit to read the pin status. for ports set for input mode, the input level of the pin can be read by reading the corresponding pi register, and data can be written to the port latch by writing to the pi register. for ports set for output mode, the port latch can be read by reading the corresponding pi register, and data can be written to the port latch by writing to the pi register. the data written to the port latch is output from the pin. the bits in the pi register correspond one for one to each port. during memory extension and microprocessor modes, the pdi registers for the pins functioning as bus _______ _______ _______ _________ ______ __________________ _________ _________ _________ control pins (a 0 to a 19 , d 0 to d 15 , cs0 to cs3, rd, wrl/wr, wrh/bhe, ale, rdy, hold, hlda, and bclk) cannot be modified. (3) pull-up control register 0 to pull-up control register 2 (pur0 to pur2 registers) figure 1.25.9 shows the pur0 to pur2 registers. the pur0 to pur2 register bits can be used to select whether or not to pull the corresponding port high in 4 bit units. the port chosen to be pulled high has a pull-up resistor connected to it when the direction bit is set for input mode. however, the pull-up control register has no effect on p0 to p3, p4 0 to p4 3 , and p5 during memory extension and microprocessor modes. although the register contents can be modified, no pull-up resis- tors are connected. (4) port control register figure 1.25.10 shows the port control register. when the p1 register is read after setting the pcr registers pcr0 bit to 1, the corresponding port latch can be read no matter how the pd1 register is set.
programmable i/o ports 211 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.25.1. i/o ports (1) p1 0 to p1 4 p1 5 to p1 7 p5 7 , p6 0 , p6 4 , p7 3 to p7 6 , p8 0 , p8 1 , p9 0 , p9 2 data bus (note 1) analog input p0 0 to p0 7 , p2 0 to p2 7 p3 0 to p3 7 , p4 0 to p4 7 , p5 0 to p5 4 , p5 6 , p11 0 to p11 7 (note 2), p12 0 to p12 7 (note 2), p13 0 to p13 7 (note 2), p14 0 , p14 1 (note 2) (inside dotted-line included) (inside dotted-line not included) "1" output data bus data bus data bus pull-up selection direction register direction register direction register direction register port latch port latch port latch port latch pull-up selection pull-up selection pull-up selection (note 1) (note 1) (note 1) port p1 control register port p1 control register input to respective peripheral functions input to respective peripheral functions note 1: symbolizes a parasitic diode. make sure the input voltage on each port will not exceed vcc. note 2: available in only the 128-pin version.
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r programmable i/o ports 212 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.25.2. i/o ports (2) p8 2 to p8 4 (note 1) p5 5 , p7 7 , p9 1 , p9 7 data bus pull-up selection direction register port latch data bus pull-up selection direction register port latch input to respective peripheral functions input to respective peripheral functions (note 1) p6 1 , p6 5 , p7 2 "1" output data bus direction register port latch pull-up selection (note 1) input to respective peripheral functions note 1: symbolizes a parasitic diode. make sure the input voltage on each port will not exceed vcc. note 2: available in only the 128-pin version. switching between cmos and nch
programmable i/o ports 213 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.25.3. i/o ports (3) p6 2 , p6 6 data bus pull-up selection direction register port latch input to respective peripheral functions (note 1) p7 0 , p7 1 data bus direction register port latch input to respective peripheral functions (note 2) output 1 p8 5 data bus (note 1) nmi interrupt input p6 3 , p6 7 output 1 data bus pull-up selection direction register port latch (note 1) switching between cmos and nch note 2: symbolizes a parasitic diode. note 1: symbolizes a parasitic diode. make sure the input voltage on each port will not exceed vcc. switching between cmos and nch
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r programmable i/o ports 214 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.25.4. i/o ports (4) p9 3 , p9 4 p9 6 p9 5 data bus direction register pull-up selection port latch analog input input to respective peripheral functions p10 0 to p10 3 (inside dotted-line not included) p10 4 to p10 7 (inside dotted-line included) d-a output enabled analog output 1 output (note) direction register direction register direction register data bus data bus data bus port latch port latch port latch analog input analog input pull-up selection pull-up selection pull-up selection input to respective peripheral functions input to respective peripheral functions d-a output enabled (note) (note) (note) 1 output note: symbolizes a parasitic diode. make sure the input voltage on each port will not exceed vcc.
programmable i/o ports 215 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.25.6. i/o pins figure 1.25.5. i/o ports (5) byte byte signal input cnv ss cnv ss signal input reset reset signal input (note 2) (note 1) (note 2) (note 1) (note 1) note 1: symbolizes a parasitic diode. make sure the input voltage on each port will not exceed vcc. note 2: a parasitic diode on the v cc side is added to the mask rom version. make sure the input voltage on each port will not exceed vcc. p8 7 p8 6 fc rf rd data bus direction register pull-up selection port latch "1" output direction register pull-up selection port latch data bus (note) (note) note: symbolizes a parasitic diode. make sure the input voltage on each port will not exceed vcc.
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r programmable i/o ports 216 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.25.7. pd0 to pd13 registers port pi direction register (i=0 to 7 and 9 to 13) (note 1, 2, 3) symbol address after reset pd0 to pd3 03e2 16 , 03e3 16 , 03e6 16 , 03e7 16 00 16 pd4 to pd7 03ea 16 , 03eb 16 , 03ee 16 , 03ef 16 00 16 pd9 to pd12 03f3 16 , 03f6 16 , 03f7 16 , 03fa 16 00 16 pd13 03fb 16 00 16 bit name functionbit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 pdi_0 p ort pi 0 direction bit pdi_1 port pi 1 direction bit pdi_2 port pi 2 direction bit pdi_3 port pi 3 direction bit pdi_4 port pi 4 direction bit pdi_5 port pi 5 direction bit pdi_6 port pi 6 direction bit pdi_7 port pi 7 direction bit 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) (i = 0 to 7 and 9 to 13) port p8 direction register symbol address after reset pd8 03f2 16 00x00000 2 bit name functionbit symbol b7 b6 b5 b4 b3 b2 b1 b0 pd8_0 port p8 0 direction bit pd8_1 port p8 1 direction bit pd8_2 port p8 2 direction bit pd8_3 port p8 3 direction bit pd8_4 port p8 4 direction bit nothing is assigned. in an attempt to write to this bit, write 0. the value, if read, turns out to be indeterminate. pd8_6 port p8 6 direction bit pd8_7 port p8 7 direction bit 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) note 1: make sure the pd9 register is written to by the next instruction after setting the prcr registers prc2 bit to 1 (write enabled). note 2: during memory extension and microprocessor modes, the pd register for the pins functioning as bus control pins (a 0 to a 19 , d 0 to d 15 , cs 0 to cs 3 , rd, wrl/wr, wrh/bhe, ale, rdy, hold, hlda and bclk) cannot be modified. note 3: to use ports p11 to p14, set the pur3 registers pu37 bit to 1 (enable). if this bit is set to 0 (disable), the p11 to p14 pins are placed in the high-impedance state. rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw (b5)
programmable i/o ports 217 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. port pi register (i=0 to 7 and 9 to 13) (note 2, 3) symbol address after reset p0 to p3 03e0 16 , 03e1 16 , 03e4 16 , 03e5 16 indeterminate p4 to p7 03e8 16 , 03e9 16 , 03ec 16 , 03ed 16 indeterminate p9 to p12 03f1 16 , 03f4 16 , 03f5 16 , 03f8 16 indeterminate p13 03f9 16 indeterminate bit name functionbit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 pi_0 port pi 0 bit pi_1 port pi 1 bit pi_2 port pi 2 bit pi_3 port pi 3 bit pi_4 port pi 4 bit pi_5 port pi 5 bit pi_6 port pi 6 bit pi_7 port pi 7 bit the pin level on any i/o port which is set for input mode can be read by reading the corresponding bit in this register. the pin level on any i/o port which is set for output mode can be controlled by writing to the corresponding bit in this register 0 : l level 1 : h level (note 1) (i = 0 to 7 and 9 to 13) port p8 register symbol address after reset p8 03f0 16 indeterminate bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 p8_0 port p8 0 bit p8_1 port p8 1 bit p8_2 port p8 2 bit p8_3 port p8 3 bit p8_4 port p8 4 bit p8_5 port p8 5 bit p8_6 port p8 6 bit p8_7 port p8 7 bit the pin level on any i/o port which is set for input mode can be read by reading the corresponding bit in this register. the pin level on any i/o port which is set for output mode can be controlled by writing to the corresponding bit in this register (except for p8 5 ) 0 : l level 1 : h level note 1: since p7 0 and p7 1 are n-channel open drain ports, the data is high-impedance. rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw ro note 2: during memory extension and microprocessor modes, the pi register for the pins functioning as bus control pins (a 0 to a 19 , d 0 to d 15 , cs 0 to cs 3 , rd, wrl/wr, wrh/bhe, ale, rdy, hold, hlda and bclk) cannot be modified. note 3: to use ports p11 to p14, set the pur3 registers pu37 bit to 1 (enable). if this bit is set to 0 (disable), the p11 to p14 registers are cleared to 00 16 and the p11 to p14 pins are placed in the high-impedance state. figure 1.25.8. p0 to p13 registers
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r programmable i/o ports 218 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. port p14 control register (128-pin package) rw b7 b6 b5 b4 b3 b2 b1 b0 p140 port p14 0 bit p141 port p14 1 bit pd140 port p14 0 direction bit pd141 port p14 1 direction bit 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) pull-up control register 3 (128-pin package) symbol address a fter reset pur3 03df 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 pu30 p11 0 to p11 3 pull-up 0 : not pulled high 1 : pulled high (note 1) pu31 p11 4 to p11 7 pull-up pu32 p12 0 to p12 3 pull-up pu33 p12 4 to p12 7 pull-up pu34 p13 0 to p13 3 pull-up pu35 p13 4 to p13 7 pull-up pu36 p14 0 , p14 1 pull-up pu37 p11 to p14 enabling bit 0 : unusable (note 2) 1 : usable symbol address a fter reset pc14 03de 16 xx00xxxx 2 bit name functionbit symbol the pin level on any i/o port which is set for input mode can be read by reading the corresponding bit in this register. the pin level on any i/o port which is set for output mode can be controlled by writing to the corresponding bit in this register 0 : l level 1 : h level nothing is assigned. in an attempt to write to this bit, write 0. the value, if read, turns out to be indeterminate. bit name functionbit symbol rw rw rw rw rw rw rw rw rw rw rw rw rw nothing is assigned. in an attempt to write to this bit, write 0. the value, if read, turns out to be indeterminate. (b3-b2) (b7-b6) note 1: the pin for which this bit is 1 (pulled high) and the direction bit is 0 (input mode) is pulled high. note 2: if the pu37 bit is set to 0 (unusable), the p11 to p14 pins are placed in the high-impedance state and the p11 to p14 registers are cleared to 0. figure 1.25.9. pc14 register and pur3 register
programmable i/o ports 219 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. pull-up control register 0 (note 1) symbol address after reset pur0 03fc 16 00 16 bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 pu00 p0 0 to p0 3 pull-up pu01 p0 4 to p0 7 pull-up pu02 p1 0 to p1 3 pull-up pu03 p1 4 to p1 7 pull-up pu04 p2 0 to p2 3 pull-up pu05 p2 4 to p2 7 pull-up pu06 p3 0 to p3 3 pull-up pu07 p3 4 to p3 7 pull-up 0 : not pulled high 1 : pulled high (note 2) pull-up control register 1 symbol address after reset(note 5) pur1 03fd 16 00000000 2 00000010 2 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 pu10 p4 0 to p4 3 pull-up (note 2) pu11 p4 4 to p4 7 pull-up (note 4) pu12 p5 0 to p5 3 pull-up (note 2) pu13 p5 4 to p5 7 pull-up (note 2) pu14 p6 0 to p6 3 pull-up pu15 p6 4 to p6 7 pull-up pu16 p7 2 to p7 3 pull-up (note 1) pu17 p7 4 to p7 7 pull-up 0 : not pulled high 1 : pulled high (note 3) note 1: the p7 0 and p7 1 pins do not have pull-ups. note 2: during memory extension and microprocessor modes, the pins are not pulled high although the contents of these bits can be modified. note 3: the pin for which this bit is 1 (pulled high) and the direction bit is 0 (input mode) is pulled high. note 4: if the pm01 to pm00 bits are set to 01 2 (memory expansion mode) or 11 2 (microprocessor mode) in a program during single-chip mode, the pu11 bit becomes 1. note 5: the values after hardware reset 1 and 2 are as follows: ? 00000000 2 when input on cnvss pin is l ? 00000010 2 when input on cnvss pin is h the values after software reset, watchdog timer reset and oscillation stop detection reset are as follows: ? 00000000 2 when pm 01 to pm00 bits of pm0 register are 00 2 (single-chip mode) ? 00000010 2 when pm 01 to pm00 bits of pm0 register are 01 2 (memory expansion mode) or 11 2 (microprocessor mode) note 1: during memory extension and microprocessor modes, the pins are not pulled high although their corresponding register contents can be modified. rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw note 2: the pin for which this bit is 1 (pulled high) and the direction bit is 0 (input mode) is pulled high. pull-up control register 2 symbol address after reset pur2 03fe 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 pu20 p8 0 to p8 3 pull-up pu21 p8 4 to p8 7 pull-up pu22 p9 0 to p9 3 pull-up pu23 p9 4 to p9 7 pull-up pu24 p10 0 to p10 3 pull-up pu25 p10 4 to p10 7 pull-up nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be 0. 0 : not pulled high 1 : pulled high (note 1) rw rw rw rw rw rw rw (b7-b6) note 1: the pin for which this bit is 1 (pulled high) and the direction bit is 0 (input mode) is pulled high. note 2: the p8 5 pin does not have pull-up. (note 2) figure 1.25.10. pur0 to pur2 registers
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r programmable i/o ports 220 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.25.11. pcr register port control register symbpl address a fter reset pcr 03ff 16 00 16 bit name functionbit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 pcr0 port p1 control bit nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be 0. rw (b7-b1) operation performed when the p1 register is read 0: when the port is set for input, the input levels of p10 to p17 pins are read. when set for output, the port latch is read. 1: the port latch is read regardless of whether the port is set for input or output.
programmable i/o ports 221 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. pin name connection ports p0 to p14 (excluding p8 5 ) x out (note 1) av ss , v ref , byte av cc after setting for input mode, connect every pin to v ss via a resistor(pull-down); or after setting for output mode, leave these pins open. (note 2) open connect to v cc connect to v ss note 1: with external clock input to x in pin. note 2: when not using all of the p11 to p14, the p11 to p14 pins may be left open by setting the pur3 registers pu37 bit to 0 (unusable) without causing any problem. nmi connect via resistor to v cc (pull-up) table 1.25.1. unassigned pin handling in single-chip mode pin name connection ports p6 to p10 (excluding p8 5 ) av ss , v ref av cc after setting for input mode, connect every pin to v ss via a resistor (pull-down); or after setting for output mode, leave these pins open. open connect to v cc connect to v ss note 1: with external clock input to x in pin. note 2: if the pm0 registers pm07 bit is set to 1 (bclk not output), connect this pin to vcc via a resistor (pulled high). note 3: when not using all of the p11 to p14, the p11 to p14 pins may be left open by setting the pur3 registers pu37 bit to 0 (unusable) without causing any problem. hold, rdy, nmi connect via resistor to v cc (pull-up) bhe, ale, hlda, x out (note 1), bclk (note 2) p4 5 / cs1 to p4 7 / cs3 connect to v cc via a resistor (pulled high) by setting the pd4 registers corresponding direction bit for csi (i=1 to 3) to 0 (input mode) and the csr registers csi bit to 0 (chip select disabled). table 1.25.2. unassigned pin handling in memory expansion mode and microprocessor mode
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r programmable i/o ports 222 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.25.12. unassigned pins handling (input mode) (input mode) (output mode) nmi x out av cc byte av ss v ref microcomputer v cc v ss in single-chip mode port p6 to p14 (except for p8 5 ) (input mode) (input mode) (output mode) nmi x out av cc av ss v ref open microcomputer v cc v ss in memory expansion mode or in microprocessor mode hold rdy ale bclk (note) bhe hlda open open open port p4 5 / cs1 to p4 7 / cs3 note 1: if the pm0 registers pm07 bit is set to 1 (bclk not output), connect this pin to vcc via a resistor (pulled high). note 2: when not using all of the p11 to p14, the p11 to p14 pins may be left open by setting the pur3 registers pu37 bit to 0 (unusable) without causing any problem. (note 2) port p0 to p14 (except for p8 5 ) (note 2)
electrical characteristics 223 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. table 1.26.1. absolute maximum ratings operating ambient temperature parameter unit v ref , x in input voltage analog supply voltage supply voltage output voltage x out v o -0.3 to v cc1 +0.3 -0.3 to v cc1 +0.3 p d power dissipation storage temperature rated value v v v condition v i av cc v cc1 , v cc2 t stg t opr symbol mw p3 0 to p3 7 , p4 0 to p4 7 , p5 0 to p5 7 , p6 0 to p6 7 , p7 2 to p7 7 , p8 0 to p8 7 , p6 0 to p6 7 , p7 2 to p7 7 , p8 0 to p8 4, p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p9 0 to p9 7 , p10 0 to p10 7 , p11 0 to p11 7 , p8 6 , p8 7 , p9 0 to p9 7 , p10 0 to p10 7 , p7 0 , p7 1 p7 0 , p7 1 -0.3 to 6.5 v v reset, cnv ss , byte, v cc1 =av cc v cc1 =av cc -0.3 to 6.5 p14 0 , p14 1 , supply voltage -0.3 to v cc1 +0.1 v v cc2 v cc2 p12 0 to p12 7 , p13 0 to p13 7 -0.3 to v cc2 +0.3 v v p11 0 to p11 7 , p14 0 , p14 1 , p3 0 to p3 7 , p4 0 to p4 7 , p5 0 to p5 7 , p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p12 0 to p12 7 , p13 0 to p13 7 -0.3 to v cc2 +0.3 v -0.3 to 6.5 -65 to 150 300 -20 to 85 / -40 to 85 -0.3 to 6.5 c topr=25 c c electrical characteristics
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r electrical characteristics 224 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. 2 . 75 . 5 typ. m a x . u n i t p a r a m e t e r v c c 1 , v c c 2 5 . 0 s u p p l y v o l t a g e ( v c c 1 v c c 2 ) s y m b o l min. standard a n a l o g s u p p l y v o l t a g e v c c 1 a v c c v v0 0 a n a l o g s u p p l y v o l t a g e s u p p l y v o l t a g e v i h i oh (avg) high average output current ma ma v s s a v s s 0 . 8 v c c 2 v v v v v v c c 2 0 . 2 v c c 2 0 . 2 v c c 1 0 0 0 l o w i n p u t v o l t a g e 0 . 1 6 v c c 2 i oh (peak) h i g h p e a k o u t p u t c u r r e n t high input voltage -5.0 -10.0 p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 ,p3 0 to p3 7 , p4 0 to p4 7 , p5 0 to p5 7 , p6 0 to p6 7 ,p7 2 to p7 7 , p8 0 to p8 4, p8 6, p8 7, p9 0 to p9 7, p10 0 to p10 7 , p 3 1 t o p 3 7 , p 4 0 t o p 4 7 , p 5 0 t o p 5 7 , p 1 2 0 t o p 1 2 7 , p 1 3 0 t o p 1 3 7 v v 0.8v cc2 0 . 5 v c c 2 v c c 2 v c c 2 ( d a t a i n p u t f u n c t i o n d u r i n g m e m o r y e x p a n s i o n a n d m i c r o p r o c e s s o r m o d e s ) p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 ( d u r i n g s i n g l e - c h i p m o d e ) p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 low peak output current 10.0 5.0 ma f ( x i n ) m a i n c l o c k i n p u t o s c i l l a t i o n f r e q u e n c y ( n o t e 4 ) l o w a v e r a g e o u t p u t c u r r e n t i ol (peak) m a i ol (avg) v p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 ,p3 0 to p3 7 , p4 0 to p4 7 , p5 0 to p5 7 , p6 0 to p6 7 ,p7 2 to p7 7 , p 8 0 t o p 8 4 , p 8 6 , p 8 7 , p 9 0 t o p 9 7 , p 1 0 0 t o p 1 0 7 , p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 ,p3 0 to p3 7 , p 4 0 t o p 4 7 , p 5 0 t o p 5 7 , p 6 0 t o p 6 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 4 , p 8 6 , p 8 7 , p 9 0 t o p 9 7 , p 1 0 0 t o p 1 0 7 , p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 4 0 t o p 4 7 , p 5 0 t o p 5 7 , p 6 0 t o p 6 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 4 , p 8 6 , p 8 7 , p 9 0 t o p 9 7 , p 1 0 0 t o p 1 0 7 , p 7 0 , p 7 1 0 . 8 v c c 1 6 . 5v v i l 20 x v cc -44 v cc =3.0 to 5.5v v cc =2.7 to 3.0v 0 0 m h z mhz 1 6 f ( x c i n )s u b - c l o c k o s c i l l a t i o n f r e q u e n c y k h z 5 0 32.768 p11 0 to p11 7 , p12 0 to p12 7 , p13 0 to p13 7 , p14 0 , p14 1 p 1 1 0 t o p 1 1 7 , p 1 2 0 t o p 1 2 7 , p 1 3 0 t o p 1 3 7 , p 1 4 0 , p 1 4 1 p 1 1 0 t o p 1 1 7 , p 1 2 0 t o p 1 2 7 , p 1 3 0 t o p 1 3 7 , p 1 4 0 , p 1 4 1 p11 0 to p11 7 , p12 0 to p12 7 , p13 0 to p13 7 , p14 0 , p14 1 n o t e 1 : r e f e r e n c e d t o v c c = v c c 1 = v c c 2 = 2 . 7 t o 5 . 5 v a t t o p r = - 2 0 t o 8 5 c / - 4 0 t o 8 5 c u n l e s s o t h e r w i s e s p e c i f i e d . n o t e 2 : t h e m e a n o u t p u t c u r r e n t i s t h e m e a n v a l u e w i t h i n 1 0 0 m s . n o t e 3 : t h e t o t a l i o l ( p e a k ) f o r p o r t s p 0 , p 1 , p 2 , p 8 6 , p 8 7 , p 9 , p 1 0 , p 1 1 , p 1 4 0 a n d p 1 4 1 m u s t b e 8 0 m a m a x . t h e t o t a l i o l ( p e a k ) f o r p o r t s p 3 , p 4 , p 5 , p 6 , p 7 , p 8 0 t o p 8 4 , p 1 2 , a n d p 1 3 m u s t b e 8 0 m a m a x . t h e t o t a l i o h ( p e a k ) f o r p o r t s p 0 , p 1 , a n d p 2 m u s t b e - 4 0 m a m a x . t h e t o t a l i o h ( p e a k ) f o r p o r t s p 3 , p 4 , p 5 , p 1 2 , a n d p 1 3 m u s t b e - 4 0 m a m a x . t h e t o t a l i o h ( p e a k ) f o r p o r t s p 6 , p 7 , a n d p 8 0 t o p 8 4 m u s t b e - 4 0 m a m a x . t h e t o t a l i o h ( p e a k ) f o r p o r t s p 8 6 , p 8 7 , p 9 , p 1 0 , p 1 1 , p 1 4 0 , a n d p 1 4 1 m u s t b e - 4 0 m a m a x . n o t e 4 : r e l a t i o n s h i p b e t w e e n m a i n c l o c k o s c i l l a t i o n f r e q u e n c y , p l l c l o c k o s c i l l a t i o n f r e q u e n c y a n d s u p p l y v o l t a g e . 0 . 8 v c c 1 vv c c 1 p 6 0 t o p 6 7 , p 7 2 t o p 7 7 , p 8 0 t o p 8 7 , p 9 0 t o p 9 7 , p 1 0 0 t o p 1 0 7 , x i n , r e s e t , c n v s s , b y t e p 1 1 0 t o p 1 1 7 , p 1 4 0 , p 1 4 1 , p 3 1 t o p 3 7 , p 4 0 t o p 4 7 , p 5 0 t o p 5 7 , p 1 2 0 t o p 1 2 7 , p 1 3 0 t o p 1 3 7 p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 ( d u r i n g s i n g l e - c h i p m o d e ) v0 . 2 v c c 2 0 ( d a t a i n p u t f u n c t i o n d u r i n g m e m o r y e x p a n s i o n a n d m i c r o p r o c e s s o r m o d e s ) p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 p 6 0 t o p 6 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 7 , p 9 0 t o p 9 7 , p 1 0 0 t o p 1 0 7 , x i n , r e s e t , c n v s s , b y t e p 1 1 0 t o p 1 1 7 , p 1 4 0 , p 1 4 1 , f ( r i n g )r i n g o s c i l l a t i o n f r e q u e n c y mhz 1 f ( p l l )p l l c l o c k o s c i l l a t i o n f r e q u e n c y ( n o t e 4 ) 46.67 x v cc - 116 v cc =3.0 to 5.5v v cc =2.7 to 3.0v 10 10 m h z m h z 2 4 f ( b c l k )c p u o p e r a t i o n c l o c k 0 m h z2 4 t s u ( p l l )p l l f r e q u e n c y s y n t h e s i z e r s t a b i l i z a t i o n w a i t t i m e v cc =5.0v v cc =3.0v 50 20 m s m s main clock input oscillation frequency 16.0 0.0 f(x in ) operating maximum frequency [mh z ] supply voltage [v] (main clock: no division) 5.53.0 10.0 2.7 aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa 20 x v cc -44mh z pll clock oscillation frequency 24.0 0.0 f(pll) operating maximum frequency [mh z ] supply voltage [v] (pll clock oscillation) 5.5 10.0 2.7 aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa 3.0 46.67 x v cc -116mh z table 1.26.2. recommended operating conditions (note 1)
electrical characteristics 225 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. table 1.26.3. a-d conversion characteristics (note 1) s t a n d a r d m i n .t y p .m a x . C i n l r e s o l u t i o n i n t e g r a l n o n - l i n e a r i t y e r r o r bits v ref =v cc1 1 0 symbol parameter measuring condition unit a n 0 t o a n 7 i n p u t a n e x 0 , a n e x 1 i n p u t e x t e r n a l o p e r a t i o n a m p c o n n e c t i o n m o d e a n 0 0 t o a n 0 7 i n p u t a n 2 0 t o a n 2 7 i n p u t v ref = v cc1 = 5v l s b 3 l s b 7 l s b v ref =v cc1 =3.3v 8 b i t 2 r l a d d e r t c o n v l a d d e r r e s i s t a n c e c o n v e r s i o n t i m e ( 1 0 b i t ) , s a m p l e & h o l d f u n c t i o n a v a i l a b l e reference voltage a n a l o g i n p u t v o l t a g e k ? s v v i a v ref v0 2 .0 1 0 v c c 1 v r e f 4 0 3 . 3 conversion time(8bit), sample & hold function available s 2.8 t c o n v t s a m p sampling time 0.3 s v ref =v cc1 v ref =v cc1 =5v, ? ad =10mhz v ref =v cc1 =5v, ? ad =10mhz d n l d i f f e r e n t i a l n o n - l i n e a r i t y e r r o r o f f s e t e r r o r g a i n e r r o r C C l s b l s b l s b 1 3 3 n o t e 1 : r e f e r e n c e d t o v c c 1 = a v c c = v r e f = 3 . 3 t o 5 . 5 v , v s s = a v s s = 0 v a t t o p r = - 2 0 t o 8 5 c / - 4 0 t o 8 5 c u n l e s s o t h e r w i s e s p e c i f i e d . n o t e 2 : i f v c c 1 > v c c 2 , d o n o t u s e a n 0 0 t o a n 0 7 a n d a n 2 0 t o a n 2 7 a s a n a l o g i n p u t p i n s . n o t e 3 : a d o p e r a t i o n c l o c k f r e q u e n c y ( ? a d f r e q u e n c y ) m u s t b e 1 0 m h z o r l e s s . a n d d i v i d e t h e f a d i f v c c 1 i s l e s s t h a n 4 . 2 v , a n d m a k e ? a d f r e q u e n c y e q u a l t o o r l o w e r t h a n f a d / 2 . n o t e 4 : a c a s e w i t h o u t s a m p l e & h o l d f u n c t i o n t u r n ? a d f r e q u e n c y i n t o 2 5 0 k h z o r m o r e i n a d d i t i o n t o a l i m i t o f n o t e 3 . a c a s e w i t h s a m p l e & h o l d f u n c t i o n t u r n ? a d f r e q u e n c y i n t o 1 m h z o r m o r e i n a d d i t i o n t o a l i m i t o f n o t e 3 . 1 0 b i t a n 0 t o a n 7 i n p u t a n e x 0 , a n e x 1 i n p u t e x t e r n a l o p e r a t i o n a m p c o n n e c t i o n m o d e a n 0 0 t o a n 0 7 i n p u t a n 2 0 t o a n 2 7 i n p u t v ref = v cc1 = 3.3v l s b 5 l s b 7 table 1.26.4. d-a conversion characteristics (note 1) table 1.26.5. flash memory version electrical characteristics (note 1) w o r d p r o g r a m t i m e b l o c k e r a s e t i m e e r a s e a l l u n l o c k e d b l o c k s t i m e l o c k b i t p r o g r a m t i m e 30 1 1 x n 30 2 0 0 4 4 x n 2 0 0 s s s s p a r a m e t e r s t a n d a r d min. t y p .m a x u n i t n o t e 1 : r e f e r e n c e d t o v c c 1 = 4 . 5 t o 5 . 5 v , 3 . 0 t o 3 . 6 v a t t o p r = 0 t o 6 0 c u n l e s s o t h e r w i s e s p e c i f i e d . n o t e 2 : n d e n o t e s t h e n u m b e r o f b l o c k e r a s e s . m i n .t y p .m a x . C C t su r o r e s o l u t i o n a b s o l u t e a c c u r a c y setup time output resistance reference power supply input current b i t s % k ? ma i vref 1 . 0 1.5 8 3 symbol parameter measuring condition unit 2010 4 s (note 2) standard note 1: referenced to v cc1 =v ref =3.3 to 5.5v, v ss =av ss =0v at topr = -20 to 85 c / -40 to 85 c unless otherwise specified. note 2: this applies when using one d-a converter, with the d-a register for the unused d-a converter set to 00 16 . the a-d converters ladder resistance is not included. also, when d-a register contents are not 00 16 , the current i vref always flows even though vref may have been set to be unconnected by the a-d control register. table 1.26.6. flash memory version program/erase voltage and read operation voltage characteristics (at topr = 0 to 60 o c) flash program, erase voltage flash read operation voltage v cc1 = 3.3 v 0.3 v or 5.0 v 0.5 v v cc1 =2.7 to 5.5 v
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r electrical characteristics 226 under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. table 1.26.7. low voltage detection circuit electrical characteristics (note 1 ) s y m b o l s t a n d a r d typ. unit m e a s u r i n g c o n d i t i o n m i n .m a x . p a r a m e t e r v d e t 4 power supply down detection voltage (notes 1, 2) v3 . 84 . 4 v c c 1 = 0 . 8 t o 5 . 5 v n o t e 1 : v d e t 4 > v d e t 3 > v d e t 2 n o t e 2 : w h e r e r e s e t l e v e l d e t e c t i o n v o l t a g e i s l e s s t h a n 2 . 7 v , i f t h e s u p p l y p o w e r v o l t a g e i s g r e a t e r t h a n t h e r e s e t l e v e l d e t e c t i o n v o l t a g e , t h e o p e r a t i o n a t f ( b c l k ) 1 0 m h z i s g u a r a n t e e d . n o t e 3 : v d e t 3 r > v d e t 3 i s n o t g u a r a n t e e d . 3 . 3 v d e t 3 reset level detection voltage (notes 1, 2) v2 . 83 . 6 2 . 2 v d e t 2 r a m r e t e n t i o n l i m i t d e t e c t i o n v o l t a g e ( n o t e s 1 , 2 ) v 2.7 0 . 8 2 . 94 . 0 2 . 0 s y m b o l s t a n d a r d typ. unit m e a s u r i n g c o n d i t i o n m i n .m a x . p a r a m e t e r 2 v cc1 =2.7 to 5.5v note : when vcc1 = 5v 1 5 0 6 (note) 5 0 t d ( r - s ) stop release time 20 td(m-l) time for internal power supply stabilization when main clock oscillation starts 20 t d ( s - r ) hardware reset 2 release wait time s ms v d e t 3 s low voltage reset retention voltage v d e t 3 r low voltage reset release voltage (note 3) 2 . 2 1.4 v v t d ( p - r ) time for internal power supply stabilization during powering-on td(e-a) low voltage detection circuit operation start time s s m s v c c 1 = 2 . 7 t o 5 . 5 v v c c 1 = v d e t 3 r t o 5 . 5 v interrupt for stop mode release cpu clock td(r-s) td(s-r) vdet3r v cc1 table 1.26.8. power supply circuit timing characteristics
electrical characteristics (vcc 1 = vcc 2 = 5v) 227 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. v cc1 = v cc2 = 5v table 1.26.9. electrical characteristics (note 1 ) s y m b o l v o h v o h h i g h o u t p u t v o l t a g e v o h v o l l o w o u t p u t v o l t a g e l o w o u t p u t v o l t a g e v o l v ol h i g h o u t p u t v o l t a g e h i g h o u t p u t v o l t a g e standard t y p . u n i t m e a s u r i n g c o n d i t i o n v v v x o u t v 2 . 0 0 . 4 5 v v x o u t 2 . 0 2 . 0 m i n .max. v c c 2 - 2 . 0 p a r a m e t e r i oh =-5ma(note 2) i oh =-1ma i oh =-200 a(note 2) i oh =-0.5ma i ol =5ma(note 2) i ol =1ma i ol =200 a(note 2) i ol =0.5ma p 6 0 t o p 6 7 , p 7 2 t o p 7 7 , p 8 0 t o p 8 4 , p 8 6 , p 8 7 , p 9 0 t o p 9 7 , h i g h p o w e r l o w p o w e r highpower l o w p o w e r h i g h p o w e r l o w p o w e r h i g h o u t p u t v o l t a g e x c o u t with no load applied with no load applied 2.5 1 . 6 v hysteresis hysteresis h i g h i n p u t c u r r e n t i i h l o w i n p u t c u r r e n t i il v r a m r a m r e t e n t i o n v o l t a g e v t + - v t - v t+- v t- c l k 0 t o c l k 4 , t a 2 o u t t o t a 4 o u t , 0.2 1.0 v 0.2 2.2 v 5 . 0 a a at stop mode 2 . 0v reset hold, rdy, ta0 in to ta4 in , a d t r g , c t s 0 t o c t s 2 , s c l , s d a , v i =5v v i =0v - 5 . 0 r fxin r f x c i n feedback resistance x in f e e d b a c k r e s i s t a n c e x c i n 1 5 1.5 m ? m ? p0 0 to p0 7 ,p1 0 to p1 7 ,p2 0 to p2 7 ,p3 0 to p3 7 , p4 0 to p4 7 ,p5 0 to p5 7 ,p6 0 to p6 7 ,p7 0 to p7 7 , p8 0 to p8 7 ,p9 0 to p9 7 ,p10 0 to p10 7, p11 0 to p11 7 , p12 0 to p12 7 ,p13 0 to p13 7 ,p14 0 ,p14 1 , x in , reset, cnvss, byte p0 0 to p0 7 ,p1 0 to p1 7 ,p2 0 to p2 7 ,p3 0 to p3 7 , p4 0 to p4 7 ,p5 0 to p5 7 ,p6 0 to p6 7 ,p7 0 to p7 7 , p8 0 to p8 7 ,p9 0 to p9 7 ,p10 0 to p10 7, p11 0 to p11 7 , p12 0 to p12 7 ,p13 0 to p13 7 ,p14 0 ,p14 1 , x in , reset, cnvss, byte r p u l l u p p u l l - u p r e s i s t a n c e 5 0k ? t b 0 i n t o t b 5 i n , i n t 0 t o i n t 5 , n m i , v x c o u t 0 0 with no load applied with no load applied highpower lowpower v i = 0 v 3 01 7 0 k i 0 t o k i 3 , r x d 0 t o r x d 2 , s i n 3 , s i n 4 p 4 0 t o p 4 7 , p 5 0 t o p 5 7 , p 1 2 0 t o p 1 2 7 , p 1 3 0 t o p 1 3 7 p 4 0 t o p 4 7 , p 5 0 t o p 5 7 , p 6 0 t o p 6 7 , p 7 2 t o p 7 7 , p8 0 to p8 4 ,p8 6 ,p8 7 ,p9 0 to p9 7 ,p10 0 to p10 7 , p0 0 to p0 7 ,p1 0 to p1 7 ,p2 0 to p2 7 ,p3 0 to p3 7 , p 1 1 0 t o p 1 1 7 , p 1 2 0 t o p 1 2 7 , p 1 3 0 t o p 1 3 7 , p 1 4 0 , p 1 4 1 v c c 2 - 0 . 3 v c c 1 - 2 . 0 v c c 1 - 2 . 0 n o t e 1 : r e f e r e n c e d t o v c c = v c c 1 = v c c 2 = 4 . 2 t o 5 . 5 v , v s s = 0 v a t t o p r = - 2 0 t o 8 5 c / - 4 0 t o 8 5 c , f ( b c l k ) = 2 4 m h z u n l e s s o t h e r w i s e s p e c i f i e d . n o t e 2 : w h e r e t h e p r o d u c t i s u s e d a t v c c 1 = 5 v a n d v c c 2 = 3 v , r e f e r t o t h e 3 v v e r s i o n v a l u e f o r t h e p i n s p e c i f i e d v a l u e o n t h e v c c 2 p o r t s i d e . v cc2 v cc2 p 1 0 0 t o p 1 0 7 , p 1 1 0 t o p 1 1 7 , p 1 4 0 , p 1 4 1 p0 0 to p0 7 ,p1 0 to p1 7 ,p2 0 to p2 7 ,p3 0 to p3 7 , i oh =-5ma i oh =-200 a p6 0 to p6 7 ,p7 2 to p7 7 ,p8 0 to p8 4 ,p8 6 ,p8 7 ,p9 0 to p9 7 , p 4 0 t o p 4 7 , p 5 0 t o p 5 7 , p 1 2 0 t o p 1 2 7 , p 1 3 0 t o p 1 3 7 p 1 0 0 t o p 1 0 7 , p 1 1 0 t o p 1 1 7 , p 1 4 0 , p 1 4 1 p0 0 to p0 7 ,p1 0 to p1 7 ,p2 0 to p2 7 ,p3 0 to p3 7 , v c c 1 - 2 . 0 v c c 1 - 0 . 3 v cc1 v cc1 v cc1 v cc1 p 6 0 t o p 6 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 4 , p 8 6 , p 8 7 , p 9 0 t o p 9 7 , p 4 0 t o p 4 7 , p 5 0 t o p 5 7 , p 1 2 0 t o p 1 2 7 , p 1 3 0 t o p 1 3 7 p 1 0 0 t o p 1 0 7 , p 1 1 0 t o p 1 1 7 , p 1 4 0 , p 1 4 1 p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 6 0 t o p 6 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 4 , p 8 6 , p 8 7 , p 9 0 t o p 9 7 , p 4 0 t o p 4 7 , p 5 0 t o p 5 7 , p 1 2 0 t o p 1 2 7 , p 1 3 0 t o p 1 3 7 p 1 0 0 t o p 1 0 7 , p 1 1 0 t o p 1 1 7 , p 1 4 0 , p 1 4 1 p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , i ol =5ma i ol =200 a 2 . 0 0 . 4 5 l o w o u t p u t v o l t a g e l o w o u t p u t v o l t a g e
electrical characteristics (vcc 1 = vcc 2 = 5v) 228 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. v cc1 = v cc2 = 5v table 1.26.10. electrical characteristics (2) (note 1 ) s y m b o l s t a n d a r d typ. unit measuring condition m i n .max. p a r a m e t e r i c c p o w e r s u p p l y c u r r e n t ( v c c = 4 . 0 t o 5 . 5 v ) n o d i v i s i o n , p l l o p e r a t i o n m a i n s i n g l e - c h i p m o d e , t h e o u t p u t p i n s a r e o p e n a n d o t h e r p i n s a r e v s s 14 20 f ( b c l k ) = 2 4 m h z , n o d i v i s i o n , p l l o p e r a t i o n m a1 8 f ( b c l k ) = 2 4 m h z , m a s k r o m 27 f l a s h m e m o r y 15 m a f l a s h m e m o r y p r o g r a m v c c = 5 . 0 v f ( b c l k ) = 1 0 m h z , 25 ma f l a s h m e m o r y e r a s e v c c = 5 . 0 v f ( b c l k ) = 1 0 m h z , t opr =25 c 3.0 a stop mode, f ( b c l k )=3 2 k h z , wait mode (note 2), oscillation capacity high 7.5 a 0.8 2 . 0 a mask rom flash memory note 1: referenced to v cc =v cc1 =v cc2 =4.2 to 5.5v, v ss =0v at topr = -20 to 85 c / -40 to 85 c, f(bclk)=24mhz unless otherwise specified. note 2: with one timer operated using f c32 . note 3: this indicates the memory in which the program to be executed exists. note 4: idet is dissipation current when the following bit is set to 1 (detection circuit enabled). idet4: vc27 bit of vcr2 register idet3: vc26 bit of vcr2 register idet2: vc25 bit of vcr2 re g ister m a1 . 8 wait mode a low power dissipation mode, rom(note 3) f ( x c i n ) = 3 2 k h z , a m a s k r o m l o w p o w e r d i s s i p a t i o n m o d e , r a m ( n o t e 3 ) f ( b c l k ) = 3 2 k h z 4 2 0 a low power dissipation mode, flash memory(note 3) f ( b c l k ) = 3 2 k h z , a f l a s h m e m o r y 2 5 ring oscillation, 5 0 m a1 n o d i v i s i o n , r i n g o s c i l l a t i o n 2 5 f ( b c l k ) = 3 2 k h z , wait mode(note 2), oscillation capacity low i d e t 4 p o w e r s u p p l y d o w n d e t e c t i o n d i s s i p a t i o n c u r r e n t ( n o t e 4 ) 4 a 0 . 7 idet3 reset area detection dissipation current (note 4) 8 a 1.2 idet2 r a m r e t e n t i o n l i m i t d e t e c t i o n d i s s i p a t i o n c u r r e n t ( n o t e 4 ) 6 a 1.1 no division, ring oscillation
electrical characteristics (vcc 1 = vcc 2 = 5v) 229 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. v cc1 = v cc2 = 5v timing requirements (v cc1 = v cc2 = 5v, v ss = 0v, at topr = 20 to 85 o c / 40 to 85 o c unless otherwise specified) table 1.26.12. memory expansion mode and microprocessor mode max. external clock rise time ns t r min. external clock input cycle time external clock input high pulse width external clock input low pulse width external clock fall time ns ns ns ns t c t w(h ) t w(l) t f parameter symbol unit standard 62.5 25 25 15 15 table 1.26.11. external clock input (note 1) (note 2) (note 3) 40 30 0 0 40 0 note 1: calculated according to the bclk frequency as follows: 40 min. data input setup time ns t su(db-rd) t su(rdy-bclk ) parametersymbol unit max. standard ns rdy input setup time data input hold time ns t h(rd-db) t h(bclk -rdy) ns rdy input hold time ns hold input setup time t su(hold-bclk ) ns hold input hold time t h(bclk-hold ) data input access time (for setting with no wait) ns t ac1(rd-db) ns ns t ac2(rd-db) t ac3(rd-db) data input access time (for setting with wait) data input access time (when accessing multiplex bus area) ns t d(bclk-hlda ) hlda output delay time f(bclk) C 45 0.5 x 10 9 [ns] note 2: calculated according to the bclk frequency as follows: f(bclk) C 45 (nC0.5) x 10 9 [ns] note 3: calculated according to the bclk frequency as follows: f(bclk) C 45 (nC0.5) x 10 9 [ns] n is 2 for 1-wait setting, 3 for 2-wait setting and 4 for 3-wait setting. n is 2 for 2-wait setting, 3 for 3-wait setting.
electrical characteristics (vcc 1 = vcc 2 = 5v) 230 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. v cc1 = v cc2 = 5v timing requirements (v cc1 = v cc2 = 5v, v ss = 0v, at topr = 20 to 85 o c / 40 to 85 o c unless otherwise specified) table 1.26.14. timer a input (gating input in timer mode) table 1.26.15. timer a input (external trigger input in one-shot timer mode) table 1.26.16. timer a input (external trigger input in pulse width modulation mode) table 1.26.17. timer a input (counter increment/decrement input in event counter mode) table 1.26.13. timer a input (counter input in event counter mode) standard max. ns tai in input low pulse width t w(tal) min. ns ns unit tai in input high pulse width t w(tah) parameter symbol t c(ta) tai in input cycle time 40 100 40 standard max. min. ns ns ns unit tai in input cycle time tai in input high pulse width tai in input low pulse width t c(ta) t w(tah) t w(tal) symbol parameter 400 200 200 standard max. min. ns ns ns unit tai in input cycle time tai in input high pulse width tai in input low pulse width t c(ta) t w(tah) t w(tal) symbol parameter 200 100 100 standard max. min. ns ns unit t w(tah) t w(tal) symbol parameter tai in input high pulse width tai in input low pulse width 100 100 standard max. min. ns ns ns unit ns ns symbol parameter tai out input cycle time tai out input high pulse width tai out input low pulse width tai out input setup time tai out input hold time t c(up) t w(uph) t w(upl) t su(up-t in ) t h(t in- up) 2000 1000 1000 400 400 standard max. min. ns ns ns unit symbol parameter tai in input cycle time tai out input setup time tai in input setup time t c(ta) t su(ta in -ta out ) t su(ta out -ta in ) 800 200 200 table 1.26.18. timer a input (two-phase pulse input in event counter mode)
electrical characteristics (vcc 1 = vcc 2 = 5v) 231 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. table 1.26.19. timer b input (counter input in event counter mode) table 1.26.20. timer b input (pulse period measurement mode) table 1.26.21. timer b input (pulse width measurement mode) table 1.26.22. a-d trigger input table 1.26.23. serial i/o _______ table 1.26.24. external interrupt inti input v cc1 = v cc2 = 5v ns ns ns ns ns ns ns standard max.min. tbi in input cycle time (counted on one edge) tbi in input high pulse width (counted on one edge) tbi in input low pulse width (counted on one edge) ns ns ns t c(tb) t w(tbh) t w(tbl) parameter symbol unit t c(tb) t w(tbl) t w(tbh) ns ns ns tbi in input high pulse width (counted on both edges) tbi in input low pulse width (counted on both edges) tbi in input cycle time (counted on both edges) standard max. min. ns ns t c(tb) t w(tbh) symbol parameter unit t w(tbl) ns tbi in input high pulse width tbi in input cycle time tbi in input low pulse width standard max. min. ns ns t c(tb) symbol parameter unit t w(tbl) ns t w(tbh) tbi in input cycle time tbi in input high pulse width tbi in input low pulse width standard max. min. ns ns t c(ad) t w(adl) symbol parameter unit ad trg input cycle time (trigger able minimum) ad trg input low pulse width standard max. min. ns ns t w(inh) t w(inl) symbol parameter unit inti input low pulse width inti input high pulse width standard max.min. clki input cycle time clki input high pulse width clki input low pulse width t c(ck) t w(ckh) t w(ckl) parametersymbol unit t d(c-q) t su(d-c) t h(c-q) txdi hold time rxdi input setup time txdi output delay time t h(c-d) rxdi input hold time 100 40 40 80 80 200 400 200 200 400 200 200 1000 125 250 250 200 100 100 0 30 90 80 timing requirements (v cc1 = v cc2 = 5v, v ss = 0v, at topr = 20 to 85 o c / 40 to 85 o c unless otherwise specified)
electrical characteristics (vcc 1 = vcc 2 = 5v) 232 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. table 1.26.25. memory expansion and microprocessor modes (for setting with no wait) v cc1 = v cc2 = 5v switching characteristics (v cc1 = v cc2 = 5v, v ss = 0v, at topr = 20 to 85 o c / 40 to 85 o c, cm15= 1 unless otherwise specified) symbol standard measuring condition max. min. parameter unit t d(bclk-ad) address output delay time 25 ns t h(bclk-ad) address output hold time (refers to bclk) 4 ns t h(bclk-cs) chip select output hold time (refers to bclk) 4 ns t d(bclk-ale) ale signal output delay time 25 ns t h(bclk-ale) ale signal output hold time C4 ns t d(bclk-rd) rd signal output delay time 25 ns t h(bclk-rd) rd signal output hold time 0 ns t d(bclk-wr) wr signal output delay time 25 ns t h(bclk-wr) wr signal output hold time 0 ns t d(bclk-db) data output delay time (refers to bclk) 40 ns t h(bclk-db) data output hold time (refers to bclk) 4 ns t h(wr-db) data output hold time (refers to wr)(note 3) ns t d(db-wr) data output delay time (refers to wr) ns note 1: calculated according to the bclk frequency as follows: f(bclk) 0.5 x 10 9 C 40 [ns] t d(bclk-cs) chip select output delay time 25 ns t h(rd-ad) address output hold time (refers to rd) 0 ns t h(wr-ad) address output hold time (refers to wr) (note 2) ns note 3: this standard value shows the timing when the output is off, and does not show hold time of data bus. hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. hold time of data bus is expressed in t = Ccr x ln (1 C v ol / v cc2 ) by a circuit of the right figure. for example, when v ol = 0.2v cc2 , c = 30pf, r = 1k ? , hold time of output l level is t = C 30pf x 1k ? x ln (1 C 0.2v cc2 / v cc2 ) = 6.7ns. dbi r c (note 1) (note 2) note 2: calculated according to the bclk frequency as follows: f(bclk) 0.5 x 10 9 [ns] figure 1.26.1 p6 p7 p8 p10 p9 p0 p1 p2 p3 p4 p5 30pf figure 1.26.1. ports p0 to p10 measurement circuit
electrical characteristics (vcc 1 = vcc 2 = 5v) 233 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. table 1.26.26. memory expansion and microprocessor modes (for 1- to 3-wait setting and external area access) v cc1 = v cc2 = 5v switching characteristics (v cc1 = v cc2 = 5v, v ss = 0v, at topr = 20 to 85 o c / 40 to 85 o c, cm15= 1 unless otherwise specified) figure 1.26.1 symbol standard measuring condition max. min. parameter unit t d(bclk-ad) address output delay time 25 ns t h(bclk-ad) address output hold time (refers to bclk) 4ns t h(bclk-cs) chip select output hold time (refers to bclk) 4 ns t d(bclk-ale) ale signal output delay time 25 ns t h(bclk-ale) ale signal output hold time C4 ns t d(bclk-rd) rd signal output delay time 25 ns t h(bclk-rd) rd signal output hold time 0 ns t d(bclk-wr) wr signal output delay time 25 ns t h(bclk-wr) wr signal output hold time 0 ns t d(bclk-db) data output delay time (refers to bclk) 40 ns t h(bclk-db) data output hold time (refers to bclk) 4 ns t h(wr-db) data output hold time (refers to wr)(note 3) ns t d(db-wr) data output delay time (refers to wr) ns note 1: calculated according to the bclk frequency as follows: f(bclk) (nC0.5) x 10 9 C 40 [ns] t d(bclk-cs) chip select output delay time 25 ns t h(rd-ad) address output hold time (refers to rd) 0 ns t h(wr-ad) address output hold time (refers to wr) (note 2) ns note 3: this standard value shows the timing when the output is off, and does not show hold time of data bus. hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. hold time of data bus is expressed in t = Ccr x ln (1 C v ol / v cc2 ) by a circuit of the right figure. for example, when v ol = 0.2v cc2 , c = 30pf, r = 1k ? , hold time of output l level is t = C 30pf x 1k ? x ln (1 C 0.2v cc2 / v cc2 ) = 6.7ns. dbi r c (note 1) (note 2) note 2: calculated according to the bclk frequency as follows: f(bclk) 0.5 x 10 9 [ns] n is 1 for 1-wait setting, 2 for 2-wait setting and 3 for 3-wait setting.
electrical characteristics (vcc 1 = vcc 2 = 5v) 234 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. table 1.26.27. memory expansion and microprocessor modes (for 2- to 3-wait setting, external area access and multiplex bus selection) v cc1 = v cc2 = 5v switching characteristics (v cc1 = v cc2 = 5v, v ss = 0v, at topr = 20 to 85 o c / 40 to 85 o c, cm15= 1 unless otherwise specified) symbol standard measuring condition max. min. parameter unit t d(bclk-ad) address output delay time 25 ns t h(bclk-ad) address output hold time (refers to bclk) 4 ns t d(bclk-cs) chip select output delay time 25 ns t h(bclk-cs) chip select output hold time (refers to bclk) 4 ns ns t h(rd-ad) address output hold time (refers to rd) (note 1) t d(bclk-rd) rd signal output delay time 25 ns t h(bclk-rd) rd signal output hold time 0 n s ns t h(wr-ad) address output hold time (refers to wr) (note 1) t d(bclk-wr) wr signal output delay time 25 ns t d(bclk-db) data output delay time (refers to bclk) 40 ns t h(bclk-db) data output hold time (refers to bclk) 4 ns t d(db-wr) data output delay time (refers to wr) (note 2) ns t d(bclk-ale) ale signal output delay time (refers to bclk) 25 ns t h(bclk-ale) ale signal output hold time (refers to bclk) C 4 ns t h(ale-ad) ale signal output hold time (refers to adderss) 30 ns t h(bclk-wr) wr signal output hold time 0 ns ns t h(rd-cs) chip select output hold time (refers to rd) (note 1) t h(wr-cs) chip select output hold time (refers to wr) (note 1) ns t d(ad-rd) rd signal output delay from the end of adress ns 0 t d(ad-wr) wr signal output delay from the end of adress ns 0 t dz(rd-ad) address output floating start time ns 8 t h(wr-db) data output hold time (refers to wr) ns (note 1) note 1: calculated according to the bclk frequency as follows: f(bclk) 0.5 x 10 9 [ns] t d(ad-ale) ale signal output delay time (refers to address) ns (note 3) note 2: calculated according to the bclk frequency as follows: f(bclk) (nC0.5) x 10 9 C40 [ns] note 3: calculated according to the bclk frequency as follows: f(bclk) 0.5 x 10 9 C25 [ns] n is 2 for 2-wait setting, 3 for 3-wait setting. figure 1.26.1
electrical characteristics (vcc 1 = vcc 2 = 5v) mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r 235 v cc1 = v cc2 = 5v under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. tai in input tai out input during event counter mode t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t h(t in Cup) t su(upCt in ) tai in input (when count on falling edge is selected) tai in input (when count on rising edge is selected) tai out input (up/down input) tbi in input t c(tb) t w(tbh) t w(tbl) t c(ad) t w(adl) ad trg input t c(ta) t su(ta in -ta out ) t su(ta out -ta in ) t su(ta out -ta in ) two-phase pulse input in event counter mode tai in input tai out input t su(ta in -ta out ) figure 1.26.2. timing diagram (1)
electrical characteristics (vcc 1 = vcc 2 = 5v) mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r 236 v cc1 = v cc2 = 5v under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.26.3. timing diagram (2) t su(dCc) clki txdi rxdi t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) t d(cCq) t h(cCd) t h(cCq) inti input
electrical characteristics (vcc 1 = vcc 2 = 5v) mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r 237 v cc1 = v cc2 = 5v under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.26.4. timing diagram (3) measuring conditions : ? v cc1 =v cc2 =5v ? input timing voltage : determined with v il =1.0v, v ih =4.0v ? output timing voltage : determined with v ol =2.5v, v oh =2.5v memory expansion mode, microprocessor mode bclk hold input hlda output p0, p1, p2, p3, p4, p5 0 to p5 2 ( common to setting with wait and setting without wait ) note: the above pins are set to high-impedance regardless of the input level of the byte pin, pm06 bit in pm0 register and pm11 bit in pm1 register. t h(bclkChold) t su(holdCbclk) ( effective for setting with wait ) t d(bclkChlda) t d(bclkChlda) hiCz rdy input tsu(rdyCbclk) th(bclkCrdy) bclk rd (multiplexed bus) (multiplexed bus) wr, wrl, wrh wr, wrl, wrh (separate bus) rd (separate bus)
electrical characteristics (vcc 1 = vcc 2 = 5v) mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r 238 v cc1 = v cc2 = 5v under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. bclk csi t d(bclk-cs) 25ns.max adi 25ns.max ale 25ns.max -4ns.min rd 25ns.max t h(bclk-rd) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min hi-z db t h(rd-db) 0ns.min 0ns.min t h(rd-ad) bhe tcyc read timing t d(bclk-ad) t d(bclk-ale) t h(bclk-ale) t su(db-rd) t d(bclk-rd) 40ns.min t ac1(rd-db) memory expansion mode, microprocessor mode ( for setting with no wait ) measuring conditions ? v cc1 =v cc2 =5v ? input timing voltage : v il =0.8v, v ih =2.0v ? output timing voltage : v ol =0.4v, v oh =2.4v wr,wrl, wrh 25ns.max t h(bclk-wr) 0ns.min bclk csi t d(bclk-cs) 25ns.max adi t d(bclk-ad) 25ns.max ale 25ns.max t d(bclk-ale) t h(bclk-ale) -4ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min tcyc t h(wr-ad) bhe t d(bclk-db) 40ns.max 4ns.min t h(bclk-db) t d(db-wr) (0.5 x tcyc-40)ns.min t h(wr-db) dbi write timing t d(bclk-wr) hi-z (0.5 x tcyc-45)ns.max tcyc= 1 f(bclk) (0.5 x tcyc)ns.min (0.5 x tcyc)ns.min figure 1.26.5. timing diagram (4)
electrical characteristics (vcc 1 = vcc 2 = 5v) mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r 239 v cc1 = v cc2 = 5v under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. bclk csi t d(bclk-cs) 25ns.max adi t d(bclk-ad) 25ns.max ale 25ns.max t h(bclk-ale) -4ns.min rd 25ns.max t h(bclk-rd) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min hi-z db t su(db-rd) 40ns.min t h(rd-db) 0ns.min tcyc bhe read timing wr,wrl, wrh 25ns.max t h(bclk-wr) 0ns.min bclk csi t d(bclk-cs) 25ns.max adi t d(bclk-ad) 25ns.max ale 25ns.max t d(bclk-ale) t h(bclk-ale) -4ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min tcyc t h(wr-ad) bhe t d(bclk-db) 40ns.max 4ns.min t h(bclk-db) t d(db-wr) (0.5 x tcyc-40)ns.min (0.5 x tcyc)ns.min t h(wr-db) dbi write timing t d(bclk-ale) t d(bclk-rd) (0.5 x tcyc)ns.min t d(bclk-wr) 0ns.min t h(rd-ad) t ac2(rd-db) hi-z memory expansion mode, microprocessor mode ( for 1-wait setting and external area access ) measuring conditions ? v cc1 =v cc2 =5v ? input timing voltage : v il =0.8v, v ih =2.0v ? output timing voltage : v ol =0.4v, v oh =2.4v (1.5 x tcyc-45)ns.max tcyc= f(bclk) 1 figure 1.26.6. timing diagram (5)
electrical characteristics (vcc 1 = vcc 2 = 5v) mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r 240 v cc1 = v cc2 = 5v under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. read timing write timing bclk csi ale db adi bhe wr, wrl wrh memory expansion mode, microprocessor mode ( for 2-wait setting and external area access ) bclk csi ale dbi adi bhe rd tcyc t d(bclk-cs) 25ns.max t d(bclk-ad) 25ns.max t d(bclk-ale) 25ns.max t h(bclk-ale) -4ns.min t d(bclk-rd) 25ns.max hi-z t su(db-rd) 40ns.min t h(rd-db) 0ns.min t h(bclk-rd) 0ns.min t h(rd-ad) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min tcyc hi-z t d(bclk-cs) 25ns.max t d(bclk-ad) 25ns.max t d(bclk-ale) 25ns.max t h(bclk-ale) -4ns.min t d(bclk-wr) 25ns.max t h(bclk-cs) 4ns.min t h(bclk-ad) 4ns.min t h(wr-ad) (0.5 x tcyc)ns.min t h(bclk-wr) 0ns.min t d(bclk-db) 40ns.max t d(db-wr) (1.5 x tcyc-40)ns.min t h(bclk-db) 4ns.min t h(wr-db) (0.5 x tcyc)ns.min measuring conditions ? v cc1 =v cc2 =5v ? input timing voltage : v il =0.8v, v ih =2.0v ? output timing voltage : v ol =0.4v, v oh =2.4v t ac2(rd-db) (2.5 x tcyc-45)ns.max tcyc= 1 f(bclk) figure 1.26.7. timing diagram (6)
electrical characteristics (vcc 1 = vcc 2 = 5v) mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r 241 v cc1 = v cc2 = 5v under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.26.8. timing diagram (7) read timing write timing bclk csi ale db adi bhe wr, wrl wrh memory expansion mode, microprocessor mode ( for 3-wait setting and external area access ) bclk csi ale dbi adi bhe rd tcyc t d(bclk-cs) 25ns.max t d(bclk-ad) 25ns.max t d(bclk-ale) 25ns.max t h(bclk-ale) -4ns.min t d(bclk-rd) 25ns.max hi-z t su(db-rd) 40ns.min t h(rd-db) 0ns.min t h(bclk-rd) 0ns.min t h(rd-ad) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min tcyc hi-z t d(bclk-cs) 25ns.max t d(bclk-ad) 25ns.max t d(bclk-ale) 25ns.max t h(bclk-ale) -4ns.min t d(bclk-wr) 25ns.max t h(bclk-cs) 4ns.min t h(bclk-ad) 4ns.min t h(wr-ad) (0.5 x tcyc)ns.min t h(bclk-wr) 0ns.min t d(bclk-db) 40ns.max t d(db-wr) (2.5 x tcyc-40)ns.min t h(bclk-db) 4ns.min t h(wr-db) (0.5 x tcyc)ns.min measuring conditions ? v cc1 =v cc2 =5v ? input timing voltage : v il =0.8v, v ih =2.0v ? output timing voltage : v ol =0.4v, v oh =2.4v t ac2(rd-db) (3.5 x tcyc-45)ns.max tcyc= 1 f(bclk)
electrical characteristics (vcc 1 = vcc 2 = 5v) mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r 242 v cc1 = v cc2 = 5v under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.26.9. timing diagram (8) memory expansion mode, microprocessor mode ( for 1- or 2-wait setting, external area access and multiplex bus selection ) bclk csi t d(bclk-cs) 25ns.max adi t d(bclk-ad) 25ns.max ale t h(bclk-ale) -4ns.min rd 25ns.max t h(bclk-rd) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min tcyc t h(rd-cs) t h(rd-ad) bhe adi /dbi t h(rd-db) 0ns.min t d(ad-ale) read timing t d(bclk-wr) 25ns.max t h(bclk-wr) 0ns.min bclk csi t d(bclk-cs) 25ns.max adi t d(bclk-ad) 25ns.max ale 25ns.max t h(bclk-ale) -4ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min tcyc t h(wr-ad) bhe t d(bclk-db) 40ns.max 4ns.min t h(bclk-db) t d(db-wr) t h(wr-db) adi /dbi data output wr,wrl, wrh write timing address (0.5 x tcyc)ns.min address data input 40ns.min (0.5 x tcyc)ns.min t d(bclk-ale) t d(bclk-rd) (0.5 x tcyc)ns.min t h(wr-cs) address t d(ad-ale) (0.5 x tcyc-25)ns.min (1.5 x tcyc-40)ns.min (0.5 x tcyc)ns.min t d(bclk-ale) (0.5 x tcyc-25)ns.min address 25ns.max t su(db-rd) t ac3(rd-db) (0.5 x tcyc)ns.min 30ns.min t d(ad-rd) 0ns.min t dz(rd-ad) 8ns.max t d(ad-wr) 0ns.min measuring conditions ? v cc1 =v cc2 =5v ? input timing voltage : v il =0.8v, v ih =2.0v ? output timing voltage : v ol =0.4v, v oh =2.4v t h(ale-ad) (1.5 x tcyc-45)ns.max tcyc= 1 f(bclk)
electrical characteristics (vcc 1 = vcc 2 = 5v) mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r 243 v cc1 = v cc2 = 5v under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.26.10. timing diagram (9) read timing write timing memory expansion mode, microprocessor mode ( for 3-wait setting, external area access and multiplex bus selection ) bclk csi ale rd adi /db adi bhe bclk csi ale adi /db tcyc t d(bclk-ad) 25ns.max tcyc data output t h(bclk-cs) 4ns.min t d(bclk-cs) 25ns.max t d(bclk-ale) 25ns.max t h(bclk-ale) -4ns.min t d(bclk-rd) 25ns.max t h(bclk-rd) 0ns.min t su(db-rd) 40ns.min t h(rd-db) 0ns.min t h(rd-ad) (0.5 x tcyc)ns.min t h(bclk-ad) 4ns.min t d(bclk-cs) 25ns.max t d(bclk-ad) 25ns.max t h(bclk-db) 4ns.min t h(bclk-wr) 0ns.min t h(wr-ad) (0.5 x tcyc)ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min t d(bclk-ale) 25ns.max t d(bclk-wr) 25ns.max t h(bclk-ale) -4ns.min t h(wr-db) (0.5 x tcyc)ns.min data input address address adi bhe wr, wrl wrh measuring conditions ? v cc1 =v cc2 =5v ? input timing voltage : v il =0.8v, v ih =2.0v ? output timing voltage : v ol =0.4v, v oh =2.4v t d(ad-ale) (0.5 x tcyc-25)ns.min t d(ad-rd) 0ns.min t dz(rd-ad) 8ns.max t ac3(rd-db) t d(bclk-db) 40ns.max aaa (0.5 x tcyc)ns.min t h(wr-cs) t d(db-wr) (2.5 x tcyc-40)ns.min t d(ad-wr) 0ns.min t h(rd-cs) (0.5 x tcyc)ns.min t d(ad-ale) (0.5 x tcyc-25)ns.min t h(ale-ad) 30ns.min (2.5 x tcyc-45)ns.max tcyc= 1 f(bclk) (no multiplex) (no multiplex)
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r electrical characteristics (vcc 1 = vcc 2 = 3v) 244 v cc1 = v cc2 = 3v under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. table 1.26.28. electrical characteristics ( note) s y m b o l v o h high output voltage v o h v o l l o w o u t p u t v o l t a g e v o l h i g h o u t p u t v o l t a g e s t a n d a r d t y p . unit m e a s u r i n g c o n d i t i o n v v x o u t v v x o u t 0 . 5 0 . 5 m i n .m a x . v cc - 0.5 p a r a m e t e r i o h = - 1 m a i o h = - 0 . 1 m a i oh = - 50 a i o l = 1 m a i o l = 0 . 1 m a i o l = 5 0 a p0 0 to p0 7 ,p1 0 to p1 7 ,p2 0 to p2 7 ,p3 0 to p3 7 , p4 0 to p4 7 ,p5 0 to p5 7 ,p6 0 to p6 7 ,p7 2 to p7 7 , p8 0 to p8 4 ,p8 6 ,p8 7 ,p9 0 to p9 7 ,p10 0 to p10 7 , highpower l o w p o w e r h i g h p o w e r l o w p o w e r h i g h p o w e r l o w p o w e r x c o u t w i t h n o l o a d a p p l i e d w i t h n o l o a d a p p l i e d 2 . 5 1.6 v h y s t e r e s i s hysteresis high input current i ih l o w i n p u t c u r r e n t i i l v ram r a m r e t e n t i o n v o l t a g e v t+- v t- v t+- v t- 0.2 0.8 v 0.2 1.8 v p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 4 0 t o p 4 7 , p 5 0 t o p 5 7 , p 6 0 t o p 6 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 7 , p 9 0 t o p 9 7 , p 1 0 0 t o p 1 0 7 , p 1 1 0 t o p 1 1 7 , p 1 2 0 t o p 1 2 7 , p 1 3 0 t o p 1 3 7 , p 1 4 0 , p 1 4 1 , 4.0 a a a t s t o p m o d e2 . 0v r e s e t x in , reset, cnvss, byte v i =3v v i = 0 v - 4 . 0 r f x i n r f x c i n f e e d b a c k r e s i s t a n c ex i n f e e d b a c k r e s i s t a n c ex c i n 2 5 3.0 m ? m ? r pullup p u l l - u p r e s i s t a n c e 1 6 0k ? v x c o u t 0 0 w i t h n o l o a d a p p l i e d w i t h n o l o a d a p p l i e d h i g h p o w e r l o w p o w e r v i =0v 6 65 0 0 c l k 0 t o c l k 4 , t a 2 o u t t o t a 4 o u t , h o l d , r d y , t a 0 i n t o t a 4 i n , a d t r g , c t s 0 t o c t s 2 , s c l , s d a , t b 0 i n t o t b 5 i n , i n t 0 t o i n t 5 , n m i , ki 0 to ki 3 , rxd 0 to rxd 2 , s in3 ,s in4 p11 0 to p11 7 ,p12 0 to p12 7 ,p13 0 to p13 7 ,p14 0 ,p14 1 p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 4 0 t o p 4 7 , p 5 0 t o p 5 7 , p 6 0 t o p 6 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 4 , p 8 6 , p 8 7 , p 9 0 t o p 9 7 , p 1 0 0 t o p 1 0 7 , p 1 1 0 t o p 1 1 7 , p 1 2 0 t o p 1 2 7 , p 1 3 0 t o p 1 3 7 , p 1 4 0 , p 1 4 1 p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 4 0 t o p 4 7 , p 5 0 t o p 5 7 , p 6 0 t o p 6 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 7 , p 9 0 t o p 9 7 , p 1 0 0 t o p 1 0 7 , p 1 1 0 t o p 1 1 7 , p 1 2 0 t o p 1 2 7 , p 1 3 0 t o p 1 3 7 , p 1 4 0 , p 1 4 1 , x in , reset, cnvss, byte p0 0 to p0 7 ,p1 0 to p1 7 ,p2 0 to p2 7 ,p3 0 to p3 7 , p 4 0 t o p 4 7 , p 5 0 t o p 5 7 , p 6 0 t o p 6 7 , p 7 2 t o p 7 7 , p8 0 to p8 4 ,p8 6 ,p8 7 ,p9 0 to p9 7 ,p10 0 to p10 7 , p11 0 to p11 7 ,p12 0 to p12 7 ,p13 0 to p13 7 ,p14 0 ,p14 1 v cc - 0.5 v cc - 0.5 n o t e : r e f e r e n c e d t o v c c = v c c 1 = v c c 2 = 2 . 7 t o 3 . 3 v , v s s = 0 v a t t o p r = - 2 0 t o 8 5 c / - 4 0 t o 8 5 c , f ( b c l k ) = 1 0 m h z u n l e s s o t h e r w i s e s p e c i f i e d . v cc v cc v cc 0 . 5 (0.7) h i g h o u t p u t v o l t a g e l o w o u t p u t v o l t a g e l o w o u t p u t v o l t a g e
electrical characteristics (vcc 1 = vcc 2 = 3v) 245 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r v cc1 = v cc2 = 3v under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. table 1.26.29. electrical characteristics (2) ( note 1) s y m b o l standard t y p . u n i t m e a s u r i n g c o n d i t i o n m i n .max. p a r a m e t e r n o d i v i s i o n m a i n s i n g l e - c h i p m o d e , t h e o u t p u t p i n s a r e o p e n a n d o t h e r p i n s a r e v s s 8 11 f(bclk)=10mhz, n o d i v i s i o n m a f(bclk)=10mhz, m a s k r o m 1 3 f l a s h m e m o r y ma 1.8 m a1 no division, ring oscillation i c c power supply current (v cc =2.7 to 3.6v) t opr =25 c 3.0 a stop mode, f(bclk)=32khz, wait mode (note 2), oscillation capacity high 6.0 a 0.7 1.8 a mask rom flash memory n o t e 1 : r e f e r e n c e d t o v c c = v c c 1 = v c c 2 = 2 . 7 t o 3 . 3 v , v s s = 0 v a t t o p r = - 2 0 t o 8 5 c / - 4 0 t o 8 5 c , f ( b c l k ) = 1 0 m h z u n l e s s o t h e r w i s e s p e c i f i e d . n o t e 2 : w i t h o n e t i m e r o p e r a t e d u s i n g f c 3 2 . n o t e 3 : t h i s i n d i c a t e s t h e m e m o r y i n w h i c h t h e p r o g r a m t o b e e x e c u t e d e x i s t s . n o t e 4 : i d e t i s d i s s i p a t i o n c u r r e n t w h e n t h e f o l l o w i n g b i t i s s e t t o 1 ( d e t e c t i o n c i r c u i t e n a b l e d ) . i d e t 4 : v c 2 7 b i t o f v c r 2 r e g i s t e r i d e t 3 : v c 2 6 b i t o f v c r 2 r e g i s t e r i d e t 2 : v c 2 5 b i t o f v c r 2 r e g i s t e r wait mode a low power dissipation mode, rom(note 3) f ( x c i n ) = 3 2 k h z , a m a s k r o m l o w p o w e r d i s s i p a t i o n m o d e , r a m ( n o t e 3 ) f ( b c l k ) = 3 2 k h z , 420 a low power dissipation mode, flash memory(note 3) f ( b c l k ) = 3 2 k h z , a f l a s h m e m o r y 2 5 ring oscillation, 45 2 5 f ( b c l k ) = 3 2 k h z , w a i t m o d e ( n o t e 2 ) , o s c i l l a t i o n c a p a c i t y l o w idet4 power supply down detection dissipation current (note 4) 4 a 0.6 i d e t 3 r e s e t l e v e l d e t e c t i o n d i s s i p a t i o n c u r r e n t ( n o t e 4 ) 2 a 0 . 4 idet2 r a m r e t e n t i o n l i m i t d e t e c t i o n d i s s i p a t i o n c u r r e n t ( n o t e 4 ) 4 a 0.9 no division, ring oscillation 8 vcc 1 =3.0v m a f l a s h m e m o r y 12 f ( b c l k ) = 1 0 m h z , p r o g r a m vcc 1 =3.0v m a f l a s h m e m o r y 2 2 f ( b c l k ) = 1 0 m h z , e r a s e
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r electrical characteristics (vcc 1 = vcc 2 = 3v) 246 v cc1 = v cc2 = 3v under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. timing requirements (v cc1 = v cc2 = 3v, v ss = 0v, at topr = 20 to 85 o c / 40 to 85 o c unless otherwise specified) table 1.26.31. memory expansion and microprocessor modes table 1.26.30. external clock input max. external clock rise time ns t r min. external clock input cycle time external clock input high pulse width external clock input low pulse width external clock fall time ns ns ns ns t c t w(h ) t w(l) t f parameter symbol unit standard 100 40 40 18 18 (note 1) (note 2) (note 3) 50 40 0 0 50 0 note 1: calculated according to the bclk frequency as follows: 40 min. data input setup time ns t su(db-rd) t su(rdy-bclk ) parametersymbol unit max. standard ns rdy input setup time data input hold time ns t h(rd-db) t h(bclk -rdy) ns rdy input hold time ns hold input setup time t su(hold-bclk ) ns hold input hold time t h(bclk-hold ) data input access time (for setting with no wait) ns t ac1(rd-db) ns ns t ac2(rd-db) t ac3(rd-db) data input access time (for setting with wait) data input access time (when accessing multiplex bus area) ns t d(bclk-hlda ) hlda output delay time f(bclk) C 60 0.5 x 10 9 [ns] note 2: calculated according to the bclk frequency as follows: f(bclk) C 60 (nC0.5) x 10 9 [ns] note 3: calculated according to the bclk frequency as follows: f(bclk) C 60 (nC0.5) x 10 9 [ns] n is 2 for 1-wait setting, 3 for 2-wait setting and 4 for 3-wait setting. n is 2 for 2-wait setting, 3 for 3-wait setting.
electrical characteristics (vcc 1 = vcc 2 = 3v) 247 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r v cc1 = v cc2 = 3v under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. timing requirements (v cc1 = v cc2 = 3v, v ss = 0v, at topr = 20 to 85 o c / 40 to 85 o c unless otherwise specified) table 1.26.33. timer a input (gating input in timer mode) table 1.26.34. timer a input (external trigger input in one-shot timer mode) table 1.26.35. timer a input (external trigger input in pulse width modulation mode) table 1.26.36. timer a input (counter increment/decrement input in event counter mode) table 1.26.32. timer a input (counter input in event counter mode) standard max. ns tai in input low pulse width t w(tal) min. ns ns unit tai in input high pulse width t w(tah) parametersymbol t c(ta) tai in input cycle time 60 150 60 standard max. min. ns ns ns unit tai in input cycle time tai in input high pulse width tai in input low pulse width t c(ta) t w(tah) t w(tal) symbol parameter 600 300 300 standard max. min. ns ns ns unit tai in input cycle time tai in input high pulse width tai in input low pulse width t c(ta) t w(tah) t w(tal) symbol parameter 300 150 150 standard max. min. ns ns unit t w(tah) t w(tal) symbol parameter tai in input high pulse width tai in input low pulse width 150 150 standard max. min. ns ns ns unit ns ns symbol parameter tai out input cycle time tai out input high pulse width tai out input low pulse width tai out input setup time tai out input hold time t c(up) t w(uph) t w(upl) t su(up-t in ) t h(t in- up) 3000 1500 1500 600 600 standard max. min. s ns ns unit symbol parameter tai in input cycle time tai out input setup time tai in input setup time t c(ta) t su(ta in -ta out ) t su(ta out -ta in ) 2 500 500 table 1.26.37. timer a input (two-phase pulse input in event counter mode)
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r electrical characteristics (vcc 1 = vcc 2 = 3v) 248 v cc1 = v cc2 = 3v under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. table 1.26.38. timer b input (counter input in event counter mode) table 1.26.39. timer b input (pulse period measurement mode) table 1.26.40. timer b input (pulse width measurement mode) table 1.26.41. a-d trigger input table 1.26.42. serial i/o _______ table 1.26.43. external interrupt inti input ns ns ns ns ns ns ns standard max.min. tbi in input cycle time (counted on one edge) tbi in input high pulse width (counted on one edge) tbi in input low pulse width (counted on one edge) ns ns ns t c(tb) t w(tbh) t w(tbl) parametersymbol unit t c(tb) t w(tbl) t w(tbh) ns ns ns tbi in input high pulse width (counted on both edges) tbi in input low pulse width (counted on both edges) tbi in input cycle time (counted on both edges) standard max. min. ns ns t c(tb) t w(tbh) symbol parameter unit t w(tbl) ns tbi in input high pulse width tbi in input cycle time tbi in input low pulse width standard max. min. ns ns t c(tb) symbol parameter unit t w(tbl) ns t w(tbh) tbi in input cycle time tbi in input high pulse width tbi in input low pulse width standard max. min. ns ns t c(ad) t w(adl) symbol parameter unit ad trg input cycle time (trigger able minimum) ad trg input low pulse width standard max. min. ns ns t w(inh) t w(inl) symbol parameter unit inti input low pulse width inti input high pulse width standard max.min. clki input cycle time clki input high pulse width clki input low pulse width t c(ck) t w(ckh) t w(ckl) parametersymbol unit t d(c-q) t su(d-c) t h(c-q) txdi hold time rxdi input setup time txdi output delay time t h(c-d) rxdi input hold time 150 60 60 160 160 300 600 300 300 600 300 300 1500 200 380 380 300 150 150 0 50 90 160 timing requirements (v cc1 = v cc2 = 3v, v ss = 0v, at topr = 20 to 85 o c / 40 to 85 o c unless otherwise specified)
electrical characteristics (vcc 1 vcc 2 = 3v) 249 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r v cc1 v cc2 = 3v under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. switching characteristics (v cc1 = v cc2 = 3v, v ss = 0v, at topr = 20 to 85 o c / 40 to 85 o c, cm15= 1 unless otherwise specified) figure 1.26.11 figure 1.26.11. ports p0 to p10 measurement circuit table 1.26.44. memory expansion, microprocessor modes (for setting with no wait) symbol standard measuring condition max. min. parameter unit t d(bclk-ad) address output delay time 30 ns t h(bclk-ad) address output hold time (refers to bclk) 4ns t h(bclk-cs) chip select output hold time (refers to bclk) 4 ns t d(bclk-ale) ale signal output delay time 30 ns t h(bclk-ale) ale signal output hold time C4 ns t d(bclk-rd) rd signal output delay time 30 ns t h(bclk-rd) rd signal output hold time 0 ns t d(bclk-wr) wr signal output delay time 30 ns t h(bclk-wr) wr signal output hold time 0 ns t d(bclk-db) data output delay time (refers to bclk) 40 ns t h(bclk-db) data output hold time (refers to bclk) 4 ns t h(wr-db) data output hold time (refers to wr)(note 3) ns t d(db-wr) data output delay time (refers to wr) ns note 1: calculated according to the bclk frequency as follows: f(bclk) 0.5 x 10 9 C 40 [ns] t d(bclk-cs) chip select output delay time 30 ns t h(rd-ad) address output hold time (refers to rd) 0 ns t h(wr-ad) address output hold time (refers to wr) (note 2) ns note 3: this standard value shows the timing when the output is off, and does not show hold time of data bus. hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. hold time of data bus is expressed in t = Ccr x ln (1 C v ol / v cc2 ) by a circuit of the right figure. for example, when v ol = 0.2v cc2 , c = 30pf, r = 1k ? , hold time of output l level is t = C 30pf x 1k ? x ln (1 C 0.2v cc2 / v cc2 ) = 6.7ns. dbi r c (note 1) (note 2) note 2: calculated according to the bclk frequency as follows: f(bclk) 0.5 x 10 9 [ns] p6 p7 p8 p10 p9 p0 p1 p2 p3 p4 p5 30pf
mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r electrical characteristics (vcc 1 vcc 2 = 3v) 250 v cc1 v cc2 = 3v under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. table 1.26.45. memory expansion and microprocessor modes (for 1- to 3-wait setting and external area access) switching characteristics (v cc1 = v cc2 = 3v, v ss = 0v, at topr = 20 to 85 o c / 40 to 85 o c, cm15= 1 unless otherwise specified) figure 1.26.11 symbol standard measuring condition max. min. parameter unit t d(bclk-ad) address output delay time 30 ns t h(bclk-ad) address output hold time (refers to bclk) 4ns t h(bclk-cs) chip select output hold time (refers to bclk) 4 ns t d(bclk-ale) ale signal output delay time 30 ns t h(bclk-ale) ale signal output hold time C4 ns t d(bclk-rd) rd signal output delay time 30 ns t h(bclk-rd) rd signal output hold time 0 ns t d(bclk-wr) wr signal output delay time 30 ns t h(bclk-wr) wr signal output hold time 0 ns t d(bclk-db) data output delay time (refers to bclk) 40 ns t h(bclk-db) data output hold time (refers to bclk) 4 ns t h(wr-db) data output hold time (refers to wr)(note 3) ns t d(db-wr) data output delay time (refers to wr) ns note 1: calculated according to the bclk frequency as follows: f(bclk) (nC0.5) x 10 9 C 40 [ns] t d(bclk-cs) chip select output delay time 30 ns t h(rd-ad) address output hold time (refers to rd) 0 ns t h(wr-ad) address output hold time (refers to wr) (note 2) ns note 3: this standard value shows the timing when the output is off, and does not show hold time of data bus. hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. hold time of data bus is expressed in t = Ccr x ln (1 C v ol / v cc2 ) by a circuit of the right figure. for example, when v ol = 0.2v cc2 , c = 30pf, r = 1k ? , hold time of output l level is t = C 30pf x 1k ? x ln (1 C 0.2v cc2 / v cc2 ) = 6.7ns. dbi r c (note 1) (note 2) note 2: calculated according to the bclk frequency as follows: f(bclk) 0.5 x 10 9 [ns] n is 1 for 1-wait setting, 2 for 2-wait setting and 3 for 3-wait setting.
electrical characteristics (vcc 1 vcc 2 = 3v) 251 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r v cc1 v cc2 = 3v under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. switching characteristics (v cc1 = v cc2 = 3v, v ss = 0v, at topr = 20 to 85 o c / 40 to 85 o c, cm15= 1 unless otherwise specified) figure 1.26.11 table 1.26.46. memory expansion and microprocessor modes (for 2- to 3-wait setting, external area access and multiplex bus selection) symbol standard measuring condition max. min. parameter unit t d(bclk-ad) address output delay time 50 ns t h(bclk-ad) address output hold time (refers to bclk) 4 ns t d(bclk-cs) chip select output delay time 50 ns t h(bclk-cs) chip select output hold time (refers to bclk) 4 ns ns t h(rd-ad) address output hold time (refers to rd) (note 1) t d(bclk-rd) rd signal output delay time 40 ns t h(bclk-rd) rd signal output hold time 0 n s ns t h(wr-ad) address output hold time (refers to wr) (note 1) t d(bclk-wr) wr signal output delay time 40 ns t d(bclk-db) data output delay time (refers to bclk) 50 ns t h(bclk-db) data output hold time (refers to bclk) 4 ns t d(db-wr) data output delay time (refers to wr) (note 2) ns t d(bclk-ale) ale signal output delay time (refers to bclk) 40 ns t h(bclk-ale) ale signal output hold time (refers to bclk) C 4 ns t h(ale-ad) ale signal output hold time (refers to adderss) 30 ns t h(bclk-wr) wr signal output hold time 0 ns ns t h(rd-cs) chip select output hold time (refers to rd) t h(wr-cs) chip select output hold time (refers to wr) (note 1) ns t d(ad-rd) rd signal output delay from the end of address ns 0 t d(ad-wr) wr signal output delay from the end of address ns 0 t dz(rd-ad) address output floating start time ns 8 t h(wr-db) data output hold time (refers to wr) ns (note 1) note 1: calculated according to the bclk frequency as follows: f(bclk) 0.5 x 10 9 [ns] t d(ad-ale) ale signal output delay time (refers to address) ns (note 3) note 2: calculated according to the bclk frequency as follows: f(bclk) (nC0.5) x 10 9 C50 [ns] note 3: calculated according to the bclk frequency as follows: f(bclk) 0.5 x 10 9 C40 [ns] n is 2 for 2-wait setting, 3 for 3-wait setting. (note 1)
electrical characteristics (vcc 1 = vcc 2 = 3v) mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r 252 v cc1 = v cc2 = 3v under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.26.12. timing diagram (1) tai in input tai out input during event counter mode tbi in input t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t c(tb) t w(tbh) t w(tbl) t c(ad) t w(adl) t h(t in Cup) t su(upCt in ) tai in input (when count on falling edge is selected) tai in input (when count on rising edge is selected) tai out input (up/down input) ad trg input t c(ta) t su(ta in -ta out ) t su(ta out -ta in ) t su(ta out -ta in ) two-phase pulse input in event counter mode tai in input tai out input t su(ta in -ta out )
electrical characteristics (vcc 1 = vcc 2 = 3v) mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r 253 v cc1 = v cc2 = 3v under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.26.13. timing diagram (2) t su(dCc) clki txdi rxdi t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) t d(cCq) t h(cCd) t h(cCq) inti input
electrical characteristics (vcc 1 = vcc 2 = 3v) mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r 254 v cc1 = v cc2 = 3v under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.26.14. timing diagram (3) measuring conditions : ? v cc1 =v cc2 =3v ? input timing voltage : determined with v il =0.6v, v ih =2.4v ? output timing voltage : determined with v ol =1.5v, v oh =1.5v memory expansion mode, microprocessor mode bclk hold input hlda output p0, p1, p2, p3, p4, p5 0 to p5 2 ( common to setting with wait and setting without wait ) note: the above pins are set to high-impedance regardless of the input level of the byte pin, pm06 bit of pm0 register and pm11 bit of pm1 register. t h(bclkChold) t su(holdCbclk) ( effective for setting with wait ) t d(bclkChlda) t d(bclkChlda) hiCz rdy input tsu(rdyCbclk) th(bclkCrdy) bclk rd (multiplexed bus) (multiplexed bus) wr, wrl, wrh wr, wrl, wrh (separate bus) rd (separate bus)
electrical characteristics (vcc 1 vcc 2 = 3v) mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r 255 v cc1 v cc2 = 3v under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.26.15. timing diagram (4) bclk csi t d(bclk-cs) 30ns.max adi 30ns.max ale 30ns.max -4ns.min rd 30ns.max t h(bclk-rd) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min hi-z db t h(rd-db) 0ns.min 0ns.min t h(rd-ad) bhe tcyc read timing t d(bclk-ad) t d(bclk-ale) t h(bclk-ale) t su(db-rd) t d(bclk-rd) 50ns.min t ac1(rd-db) memory expansion mode, microprocessor mode ( for setting with no wait ) measuring conditions ? v cc1 =v cc2 =3v ? input timing voltage : v il =0.6v, v ih =2.4v ? output timing voltage : v ol =1.5v, v oh =1.5v wr,wrl, wrh 30ns.max t h(bclk-wr) 0ns.min bclk csi t d(bclk-cs) 30ns.max adi t d(bclk-ad) 30ns.max ale 30ns.max t d(bclk-ale) t h(bclk-ale) -4ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min tcyc t h(wr-ad) bhe t d(bclk-db) 40ns.max 4ns.min t h(bclk-db) t d(db-wr) (0.5 x tcyc-40)ns.min t h(wr-db) dbi write timing t d(bclk-wr) hi-z (0.5 x tcyc-60)ns.max tcyc= 1 f(bclk) (0.5 x tcyc)ns.min (0.5 x tcyc)ns.min
electrical characteristics (vcc 1 vcc 2 = 3v) mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r 256 v cc1 v cc2 = 3v under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.26.16. timing diagram (5) bclk csi t d(bclk-cs) 30ns.max adi t d(bclk-ad) 30ns.max ale 30ns.max t h(bclk-ale) -4ns.min rd 30ns.max t h(bclk-rd) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min hi-z db t su(db-rd) 50ns.min t h(rd-db) 0ns.min tcyc bhe read timing wr,wrl, wrh 30ns.max t h(bclk-wr) 0ns.min bclk csi t d(bclk-cs) 30ns.max adi t d(bclk-ad) 30ns.max ale 30ns.max t d(bclk-ale) t h(bclk-ale) -4ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min tcyc t h(wr-ad) bhe t d(bclk-db) 40ns.max 4ns.min t h(bclk-db) t d(db-wr) (0.5 x tcyc-40)ns.min (0.5 x tcyc)ns.min t h(wr-db) dbi write timing t d(bclk-ale) t d(bclk-rd) (0.5 x tcyc)ns.min t d(bclk-wr) 0ns.min t h(rd-ad) t ac2(rd-db) hi-z memory expansion mode, microprocessor mode ( for 1-wait setting and external area access ) measuring conditions ? v cc1 =v cc2 =3v ? input timing voltage : v il =0.6v, v ih =2.4v ? output timing voltage : v ol =1.5v, v oh =1.5v (1.5 x tcyc-60)ns.max tcyc= 1 f(bclk)
electrical characteristics (vcc 1 vcc 2 = 3v) mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r 257 v cc1 v cc2 = 3v under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.26.17. timing diagram (6) read timing write timing bclk csi ale db adi bhe wr, wrl wrh memory expansion mode, microprocessor mode ( for 2-wait setting and external area access ) bclk csi ale dbi adi bhe rd tcyc t d(bclk-cs) 30ns.max t d(bclk-ad) 30ns.max t d(bclk-ale) 30ns.max t h(bclk-ale) -4ns.min t d(bclk-rd) 30ns.max hi-z t su(db-rd) 50ns.min t h(rd-db) 0ns.min t h(bclk-rd) 0ns.min t h(rd-ad) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min tcyc hi-z t d(bclk-cs) 30ns.max t d(bclk-ad) 30ns.max t d(bclk-ale) 30ns.max t h(bclk-ale) -4ns.min t d(bclk-wr) 30ns.max t h(bclk-cs) 4ns.min t h(bclk-ad) 4ns.min t h(wr-ad) (0.5 x tcyc)ns.min t h(bclk-wr) 0ns.min t d(bclk-db) 40ns.max t d(db-wr) (1.5 x tcyc-40)ns.min t h(bclk-db) 4ns.min t h(wr-db) (0.5 x tcyc)ns.min measuring conditions ? v cc1 =v cc2 =3v ? input timing voltage : v il =0.6v, v ih =2.4v ? output timing voltage : v ol =1.5v, v oh =1.5v t ac2(rd-db) (2.5 x tcyc-60)ns.max tcyc= 1 f(bclk)
electrical characteristics (vcc 1 vcc 2 = 3v) mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r 258 v cc1 v cc2 = 3v under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.26.18. timing diagram (7) read timing write timing bclk csi ale db adi bhe wr, wrl wrh memory expansion mode, microprocessor mode ( for 3-wait setting and external area access ) bclk csi ale dbi adi bhe rd tcyc t d(bclk-cs) 30ns.max t d(bclk-ad) 30ns.max t d(bclk-ale) 30ns.max t h(bclk-ale) -4ns.min t d(bclk-rd) 30ns.max hi-z t su(db-rd) 50ns.min t h(rd-db) 0ns.min t h(bclk-rd) 0ns.min t h(rd-ad) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min tcyc hi-z t d(bclk-cs) 30ns.max t d(bclk-ad) 30ns.max t d(bclk-ale) 30ns.max t h(bclk-ale) -4ns.min t d(bclk-wr) 30ns.max t h(bclk-cs) 4ns.min t h(bclk-ad) 4ns.min t h(wr-ad) (0.5 x tcyc)ns.min t h(bclk-wr) 0ns.min t d(bclk-db) 40ns.max t d(db-wr) (2.5 x tcyc-40)ns.min t h(bclk-db) 4ns.min t h(wr-db) (0.5 x tcyc)ns.min measuring conditions ? v cc1 =v cc2 =3v ? input timing voltage : v il =0.6v, v ih =2.4v ? output timing voltage : v ol =1.5v, v oh =1.5v t ac2(rd-db) (3.5 x tcyc-60)ns.max tcyc= 1 f(bclk)
electrical characteristics (vcc 1 vcc 2 = 3v) mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r 259 v cc1 v cc2 = 3v under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.26.19. timing diagram (8) memory expansion mode, microprocessor mode ( for 2-wait setting, external area access and multiplex bus selection ) bclk csi t d(bclk-cs) 40ns.max adi t d(bclk-ad) 40ns.max ale t h(bclk-ale) -4ns.min rd 40ns.max t h(bclk-rd) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min tcyc t h(rd-cs) t h(rd-ad) bhe adi /dbi t h(rd-db) 0ns.min t d(ad-ale) read timing t d(bclk-wr) 40ns.max t h(bclk-wr) 0ns.min bclk csi t d(bclk-cs) 40ns.max adi t d(bclk-ad) 40ns.max ale 40ns.max t h(bclk-ale) -4ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min tcyc t h(wr-ad) bhe t d(bclk-db) 50ns.max 4ns.min t h(bclk-db) t d(db-wr) t h(wr-db) adi /dbi data output wr,wrl, wrh write timing address (0.5 x tcyc)ns.min address data input 50ns.min (0.5 x tcyc)ns.min t d(bclk-ale) t d(bclk-rd) (0.5 x tcyc)ns.min t h(wr-cs) address t d(ad-ale) (0.5 x tcyc-40)ns.min (1.5 x tcyc-50)ns.min (0.5 x tcyc)ns.min t d(bclk-ale) (0.5 x tcyc-40)ns.min address 40ns.max t su(db-rd) t ac3(rd-db) (0.5 x tcyc)ns.min t h(ale-ad) 30ns.min t d(ad-rd) 0ns.min t dz(rd-ad) 8ns.max t d(ad-wr) 0ns.min measuring conditions ? v cc1 =v cc2 =3v ? input timing voltage : v il =0.6v, v ih =2.4v ? output timing voltage : v ol =1.5v, v oh =1.5v (1.5 x tcyc-60)ns.max tcyc= 1 f(bclk)
electrical characteristics (vcc 1 vcc 2 = 3v) mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r 260 v cc1 v cc2 = 3v under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.26.20. timing diagram (9) read timing write timing memory expansion mode, microprocessor mode ( for 3-wait setting, external area access and multiplex bus selection ) bclk csi ale rd adi /db adi bhe bclk csi ale adi /db tcyc t d(bclk-ad) 40ns.max tcyc data output t h(bclk-cs) 6ns.min t d(bclk-cs) 40ns.max t d(bclk-ale) 40ns.max t h(bclk-ale) -4ns.min t d(bclk-rd) 40ns.max t h(bclk-rd) 0ns.min t su(db-rd) 50ns.min t h(rd-db) 0ns.min t h(rd-ad) (0.5 x tcyc)ns.min t h(bclk-ad) 4ns.min t d(bclk-cs) 40ns.max t d(bclk-ad) 40ns.max t h(bclk-db) 4ns.min t h(bclk-wr) 0ns.min t h(wr-ad) (0.5 x tcyc)ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min t d(bclk-ale) 40ns.max t d(bclk-wr) 40ns.max t h(wr-db) (tcyc/2)ns.min data input address address adi bhe wr, wrl wrh measuring conditions ? v cc1 =v cc2 =3v ? input timing voltage : v il =0.6v, v ih =2.4v ? output timing voltage : v ol =1.5v, v oh =1.5v t h(ale-ad) 30ns.min t d(ad-ale) (0.5 x tcyc-40)ns.min t d(ad-rd) 0ns.min t dz(rd-ad) 8ns.max t ac3(rd-db) t d(bclk-db) 50ns.max (0.5 x tcyc)ns.min t h(wr-cs) t d(db-wr) (2.5 x tcyc-50)ns.min t d(ad-wr) 0ns.min t h(rd-cs) (0.5 x tcyc)ns.min t d(ad-ale) (0.5 x tcyc-40)ns.min (2.5 x tcyc-60)ns.max tcyc= 1 f(bclk) t h(bclk-ale) -4ns.min (no multiplex) (no multiplex)
flash memory version 261 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. table 1.27.1. flash memory version specifications flash memory version flash memory performance the flash memory version is functionally the same as the mask rom version except that it internally con- tains flash memory. the flash memory version has three modescpu rewrite, standard serial input/output, and parallel input/ output modesin which its internal flash memory can be operated on. table 1.27.1 shows the outline performance of flash memory version (see table 1.1.1 for the items not listed in table 1.27.1.). item flash memory operating mode erase block method for program method for erasure program, erase control method protect method number of commands number of program and erasure rom code protection specification 3 modes (cpu rewrite, standard serial i/o, parallel i/o) see figure 1.27.1 1 block (4 kbytes) (note 1) in units of word, in units of byte (note 2) collective erase, block erase program and erase controlled by software command protected for each block by lock bit 8 commands 100 times parallel i/o and standard serial i/o modes are supported. note 1: the boot rom area contains a standard serial i/o mode rewrite control program which is stored in it when shipped from the factory. this area can only be rewritten in parallel input/output mode. note 2: can be programmed in byte units in only parallel input/output mode. user rom area boot rom area data retention 10 years table 1.27.2. flash memory rewrite modes overview flash memory cpu rewrite mode standard serial i/o mode parallel i/o mode rewrite mode function areas which user rom area user rom area user rom area can be rewritten boot rom area operation single chip mode boot mode parallel i/o mode mode memory expansion mode (ew0 mode) boot mode (ew0 mode) rom none serial programmer parallel programmer programmer the user rom area is rewrit- ten by executing software commands from the cpu. ew0 mode: can be rewritten in any area other than the flash memory ew1 mode: can be rewritten in the flash memory the user rom area is rewrit- ten by using a dedicated se- rial programmer. standard serial i/o mode 1: clock sync serial i/o standard serial i/o mode 2: uart the boot rom and user rom areas are rewritten by using a dedicated parallel programmer.
flash memory version 262 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. 1. memory map the rom in the flash memory version is separated between a user rom area and a boot rom area. figure 1.27.1 shows the block diagram of flash momoery. the user rom area has a 4k-byte block a, in addition to the area that stores a program for microcomputer operation during singe-chip or memory expan- sion mode. the user rom area is divided into several blocks, each of which can individually be protected (locked) against programming or erasure. the user rom area can be rewritten in all of cpu rewrite, standard serial input/output, and parallel input/output modes. block a is enabled for use by setting the pm1 registers pm10 bit to 1 (block a enabled, cs2 area at addresses 10000 16 to 26fff 16 ). the boot rom area is located at addresses that overlap the user rom area, and can only be rewritten in parallel input/output mode. after a hardware reset that is performed by applying a high-level signal to the cnv ss and p5 0 pins and a low-level signal to the p5 5 pin, the program in the boot rom area is executed. after a hardware reset that is performed by applying a low-level signal to the cnv ss pin, the program in the user rom area is executed (but the boot rom area cannot be read). figure 1.27.1. flash memory block diagram 00ffff 16 block a :4k bytes 00f000 16 4k bytes 0ff000 16 0fffff 16 boot rom area note 1: the boot rom area can only be rewritten in parallel input/output mode. note 2: to specify a block, use an even address in that block. note 3: shown here is a block diagram during single-chip mode. note 4: block a can be made usable by setting the pm1 registers pm10 bit to 1 (block a enabled, cs2 area allocated at addresses 10000 16 to 26fff 16 ). block a cannot be erased by the erase all unlocked block command. use the block erase command to erase it. 0f0000 16 block 0 to block 5 (32+8+8+8 +4+4)k bytes 0e0000 16 block 6 : 64k bytes 0effff 16 0d0000 16 block 7 : 64k bytes 0dffff 16 0c0000 16 block 8 : 64k bytes 0cffff 16 0b0000 16 block 9 : 64k bytes 0bffff 16 0a0000 16 block 10 : 64k bytes 0affff 16 0fffff 16 0ff000 16 0fffff 16 block 0 : 4k bytes block 1 : 4k bytes block 2 : 8k bytes 0fe000 16 0fefff 16 0fc000 16 0fdfff 16 block 3 : 8k bytes 0fa000 16 0fbfff 16 block 4 : 8k bytes 0f8000 16 0f9fff 16 block 5 : 32k bytes 0f0000 16 0f7fff 16 user rom area 090000 16 block 11 : 64k bytes 09ffff 16 080000 16 block 12 : 64k bytes 08ffff 16
flash memory 263 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. boot mode after a hardware reset which is performed by applying a low-level signal to the p5 5 pin and a high-level signal to the cnv ss and p5 0 pins, the microcomputer is placed in boot mode, thereby executing the pro- gram in the boot rom area. during boot mode, the boot rom and user rom areas are switched over by the fmr05 bit in the fmr0 register. the boot rom area contains a standard serial input/output mode based rewrite control program which was stored in it when shipped from the factory. the boot rom area can be rewritten in parallel input/output mode. prepare an ew0 mode based rewrite control program and write it in the boot rom area, and the flash memory can be rewritten as suitable for the system. functions to prevent flash memory from rewriting to prevent the flash memory from being read or rewritten easily, parallel input/output mode has a rom code protect and standard serial input/output mode has an id code check function. rom code protect function the rom code protect function inhibits the flash memory from being read or rewritten during parallel input/output mode. figure 1.27.2 shows the romcp register. the romcp register is located in the user rom area.the romcp1 bit consists of two bits. the rom code protect function is enabled by clearing one or both of two romcp1 bits to 0 when the romcr bits are not 00 2 , with the flash memory thereby protected against reading or rewriting. conversely, when the romcr bits are 00 2 (rom code protect removed), the flash memory can be read or rewritten. once the rom code protect function is enabled, the romcr bits cannot be changed during parallel input/output mode. therefore, use standard serial input/output or other modes to rewrite the flash memory. id code check function use this function in standard serial input/output mode. unless the flash memory is blank, the id codes sent from the programmer and the id codes written in the flash memory are compared to see if they match. if the id codes do not match, the commands sent from the programmer are not accepted. the id code consists of 8-bit data, the areas of which, beginning with the first byte, are 0fffdf 16 , 0fffe3 16 , 0fffeb 16 , 0fffef 16 , 0ffff3 16 , 0ffff7 16 , and 0ffffb 16 . prepare a program in which the id codes are preset at these addresses and write it in the flash memory.
flash memory 264 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.27.2. romcp register figure 1.27.3. address for id code stored symbol address value when shipped romcp 0fffff 16 ff 16 (note 4) rom code protect control address bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 00: removes protect 01: 10: 11: 00: 01: 10: 11: protect disabled rom code protect reset bit (note 2, note 4) rom code protect level 1 set bit (note 1, note 3, note 4) romcr romcp1 b5 b4 b7 b6 11 reserved bit set this bit to 1 reserved bit set this bit to 1 reserved bit set this bit to 1 reserved bit set this bit to 1 enables roomcp1 bit } protect enabled } note 1: if the romcr bits are set to other than 00 2 and the romcp1 bits are set to other than 11 2 ( rom code protect enabled), the flash memory is disabled against reading and rewriting in parallel input/output mode. note 2: if the romcr bits are set to 00 2 when the romcr bits are other than 00 2 and the romcp1 bits are other than 11 2 , rom code protect level 1 is removed. however, because the romcr bits cannot be modified during parallel input/output mode, they need to be modified in standard serial input/output or other modes. note 3: the romcp1 bits are effective when the romcr bits are 01 2 , 10 2 , or 11 2 . note 4: once any of these bits is cleared to 0, it cannot be set back to 1. if a memory block that contains the romcp register is erased, the romcp register is set to ff 16 . 11 rw rw rw rw rw rw rw rw rw reset vector watchdog timer vector single step vector address match vector brk instruction vector overflow vector undefined instruction vector id7 id6 id5 id4 id3 id2 id1 dbc vector nmi vector 0fffff 16 to 0ffffc 16 0ffffb 16 to 0ffff8 16 0ffff7 16 to 0ffff4 16 0ffff3 16 to 0ffff0 16 0fffef 16 to 0fffec 16 0fffeb 16 to 0fffe8 16 0fffe7 16 to 0fffe4 16 0fffe3 16 to 0fffe0 16 0fffdf 16 to 0fffdc 16 4 bytes address romcp
flash memory 265 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. cpu rewrite mode in cpu rewrite mode, the user rom area can be rewritten by executing software commands from the cpu. therefore, the user rom area can be rewritten directly while the microcomputer is mounted on-board without having to use a rom programmer, etc. in cpu rewrite mode, only the user rom area shown in figure 1.27.1 can be rewritten and the boot rom area cannot be rewritten. make sure the program and the block erase commands are executed only on each block in the user rom area. during cpu rewrite mode, the user rom area be operated on in either erase write 0 (ew0) mode or erase write 1 (ew1) mode. table 1.27.3 lists the differences between erase write 0 (ew0) and erase write 1 (ew1) modes. table 1.27.3. ew0 mode and ew1 mode item ew0 mode ew1 mode operation mode ? single chip mode single chip mode ? memory expansion mode ? boot mode areas in which a ? user rom area user rom area rewrite control ? boot rom area program can be located areas in which a must be transferred to any area other can be executed directly in the user rewrite control than the flash memory (e.g., ram) rom area program can be executed before being executed areas which can be user rom area user rom area rewritten however, this does not include the area in which a rewrite control program exists software command none ? program, block erase command limitations cannot be executed on any block in which a rewrite control program exists ? erase all unlocked block command cannot be executed when the lock bit for any block in which a rewrite control program exists is set to 1 (unlocked) or the fmr0 registers fmr02 bit is set to 1 (lock bit disabled) ? read status register command cannot be executed modes after program or read status register mode read array mode erase cpu status during auto operating hold state (i/o ports retain the state in write and auto erase which they were before the command was executed) (note) flash memory status ? read the fmr0 register's fmr00, read the fmr0 register's fmr00, detection fmr06, and fmr07 bits in a fmr06, and fmr07 bits in a program program ? execute the read status register command to read the status register's sr7, sr5, and sr4 flags. _______ note: make sure no interrupts (except nmi and watchdog timer interrupts) and dma transfers will occur.
flash memory 266 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. ew0 mode the microcomputer is placed in cpu rewrite mode by setting the fmr0 registers fmr01 bit to 1 (cpu rewrite mode enabled), ready to accept commands. in this case, because the fmr1 registers fmr11 bit = 0, ew0 mode is selected. the fmr01 bit can be set to 1 by writing 0 and then 1 in succession. use software commands to control program and erase operations. read the fmr0 register or status register to check the status of program or erase operation at completion. ew1 mode ew1 mode is selected by setting fmr11 bit to 1 (by writing 0 and then 1 in succession) after setting the fmr01 bit to 1 (by writing 0 and then 1 in succession). read the fmr0 register to check the status of program or erase operation at completion. the status register cannot be read during ew1 mode.
flash memory 267 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.27.4 shows the fidr, fmr0 and fmr1 registers. fmr00 bit this bit indicates the operating status of the flash memory. the bit is 0 when the program, erase, or lock bit program is running; otherwise, the bit is 1. fmr01 bit the microcomputer is made ready to accept commands by setting the fmr01 bit to 1 (cpu rewrite mode). during boot mode, make sure the fmr05 bit also is 1 (user rom area access). fmr02 bit the lock bit set for each block can be disabled by setting the fmr02 bit to 1 (lock bit disabled). (refer to the description of the data protect function.) the lock bits set are enabled by setting the fmr02 bit to 0. the fmr02 bit only disables the lock bit function and does not modify the lock bit data (lock bit status flag). however, if the erase command is executed while the fmr02 bit is set to 1, the lock bit data changes state from 0 (locked) to 1 (unlocked) after erase is completed. fmstp bit this bit is provided for initializing the flash memory control circuits, as well as for reducing the amount of current consumed in the flash memory. the internal flash memory is disabled against access by setting the fmstp bit to 1. therefore, the fmstp bit must be written to by a program in other than the flash memory. in the following cases, set the fmstp bit to 1: ? when flash memory access resulted in an error while erasing or programming in ew0 mode (fmr00 bit not reset to 1 (ready)) ? when entering low power mode or ring low power mode figure 1.27.7 shows a flow chart to be followed before and after entering low power mode. note that when going to stop or wait mode, the fmr0 register does not need to be set because the power for the internal flash memory is automatically turned off and is turned back on again after returning from stop or wait mode. fmr05 bit this bit switches between the boot rom and user rom areas during boot mode. set this bit to 0 when accessing the boot rom area (for read) or 1 (user rom access) when accessing the user rom area (for read, write, or erase). fmr06 bit this is a read-only bit indicating the status of auto program operation. the bit is set to 1 when a program error occurs; otherwise, it is cleared to 0. for details, tefer to the description of the full status check. fmr07 bit this is a read-only bit indicating the status of auto erase operation. the bit is set to 1 when an erase error occurs; otherwise, it is cleared to 0. for details, tefer to the description of the full status check. figure 1.27.5 and 1.27.6 show the setting and resetting of ew0 mode and ew1 mode, respectively. fmr11 bit setting this bit to 1 places the microcomputer in ew1 mode. fmr16 bit this is a read-only bit indicating the execution result of the read lock bit status command.
flash memory 268 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. flash memory control register 0 symbol address after reset fmr0 01b7 16 xx000001 2 b7 b6 b5 b4 b3 b2 b1 b0 fmr00 bit symbol bit name function rw 0: busy (being written or erased) 1: ready cpu rewrite mode select bit (note 1) 0: disables cpu rewrite mode 1: inables cpu rewrite mode fmr01 0: boot rom area is accessed 1: user rom area is accessed lock bit disable select bit (note 2) 0: inables lock bit 1: disables lock bit flash memory stop bit (note 3, note 5)) user rom area select bit (note 3) (effective in only boot mode) fmr02 fmstp fmr05 0 ry/by status flag reserved bit must always be set to 0 0: terminated normally 1: terminated in error program status flag (note 4) fmr06 0: terminated normally 1: terminated in error erase status flag (note 4) fmr07 flash memory control register 1 symbol address after reset fmr1 01b5 16 0x00xx0x 2 b7 b6 b5 b4 b3 b2 b1 b0 bit symbol bit name function ew1 mode select bit ( note) 0: ew0 mode 1: ew1 mode fmr11 0 reserved bit must always be set to 0 reserved bit the value in this bit when read is indeterminate. reserved bit must always be set to 0 0: lock 1: unlock lock bit status flag fmr06 000 rw rw rw rw rw ro ro ro ro rw ro rw rw rw (b0) (b5-b4) (b7) (b4) 0: enables flash memory operation 1: stops flash memory operation (placed in low power mode, flash memory initialized) note 1: to set this bit to 1, write 0 and then 1 in succession. make sure no interrupts or dma transfers will occur before writing 1 after writing 0. write to this bit when the nmi pin is in the high state. also, while in ew0 mode, write to this bit from a program in other than the flash memory. note 2: to set this bit to 1, write 0 and then 1 in succession when the fmr01 bit = 1. make sure no interrupts or no dma transfers will occur before writing 1 after writing 0. note 3: write to this bit from a program in other than the flash memory. note 4: this flag is cleared to 0 by executing the clear status command. note 5: effective when the fmr01 bit = 1 (cpu rewrite mode). if the fmr01 bit = 0, although the fmr03 bit can be set to 1 by writing 1 in a program, the flash memory is neither placed in low power mode nor initialized. note 6: this status includes writing or reading with the lock bit program or read lock bit status command. reserved bit the value in this bit when read is indeterminate. (b3-b2) ro note : to set this bit to 1, write 0 and then 1 in succession when the fmr01 bit = 1. make sure no interrupts or no dma transfers will occur before writing 1 after writing 0. the fmr01 and fmr11 bits both are cleared to 0 by setting the fmr01 bit to 0. flash identification register symbol address a fter reset fidr 01b4 16 xxxxxx00 2 b7 b6 b5 b4 b3 b2 b1 b0 fidr0 bit symbol bit name function rw 0 0: m16c/62n, m3062gf8n type flash module 1 0: m16c/62p type flash module 1 1: m16c/62m, m16c/62a type flash module flash module type identification value note: this register identifies on-chip flash module type of m16c/62 group. note, however, no chip version is known by this register. follow the procedure described below for the identification. (1) write ff 16 to fidr register (2) read fidr register (3) check two low-order bits of read value make sure no access to external memories or other sfrs or no interrupts or dma transfers will occur between the above two instructions no. 1 and no. 2. fidr1 nothing is assigned. when write, set to 0. when read, their contents are indeterminate. (b7-b2) b1 b0 ro ro figure 1.27.4. fidr register and fmr0 and fmr1 registers
flash memory 269 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. execute the read array command single-chip mode, memory expansion mode, or boot mode set cm0, cm1, and pm1 registers (note 1) execute software commands jump to the rewrite control program which has been transferred to any area other than the flash memory (the subsequent processing is executed by the rewrite control program in any area other than the flash memory) transfer a cpu rewrite mode based rewrite control program to any area other than the flash memory for only boot mode write 0 to the fmr05 bit (boot rom area accessed) (note 4) write 0 to the fmr01 bit (cpu rewrite mode disabled) for only boot mode set the fmr05 bit to 1 (user rom area access) set the fmr01 bit by writing 0 and then 1 (cpu rewrite mode enabled) (note 2) ew0 mode operation procedure rewrite control program jump to a specified address in the flash memory note 1: select 10 mhz or less for cpu clock using the cm0 registers cm06 bit and cm1 registers cm17 to 6 bits. also, set the pm1 registers pm17 bit to 1 (with wait state). note 2: to set the fmr01 bit to 1, write 0 and then 1 in succession. make sure no interrupts or no dma transfers will occur before writing 1 after writing 0. write to the fmr01 bit from a program in other than the flash memory. also write only when the nmi pin is h level. note 3: disables the cpu rewrite mode after executing the read array command. note 4: user rom area is accessed when the fmr05 bit is set to 1. figure 1.27.5. setting and tesetting of ew0 mode
flash memory 270 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.27.6. setting and resetting of ew1 mode single-chip mode (note 1) set cm0, cm1, and pm1 registers (note 2) set the fmr01 bit by writing 0 and then 1 (cpu rewrite mode enabled) set the fmr11 bit by writing 0 and then 1 (ew1 mode) (note 3) program in rom ew1 mode operation procedure execute software commands write 0 to the fmr01 bit (cpu rewrite mode disabled) note 1: in ew1 mode, do not set the microcomputer in memory expansion or boot mode. note 2: select 10 mhz or less for cpu clock using the cm0 registers cm06 bit and cm1 registers cm17 to 6 bits. also, set the pm1 registers pm17 bit to 1 (with wait state). note 2: to set the fmr01 bit to 1, write 0 and then 1 in succession. make sure no interrupts or no dma transfers will occur before writing 1 after writing 0. write to the fmr01 bit from a program in other than the flash memory. also write only when the nmi pin is h level.
flash memory 271 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.27.7. processing before and after low power sissipation mode turn main clock on transfer a low power dissipation mode program to any area other the flash memory switch the clock source for cpu clock. turn main clock off. (note 2) jump to the low power dissipation mode program which has been transferred to any area other the flash memory. (the subsequent processing is executed by a program in any area other than the flash memory.) wait until the flash memory circuit stabilizes (15 s) (note 3) set the fmstp bit to 0 (flash memory operation) set fmstp bit to 1 (flash memory stopped. low power state)(note 1) process of low power dissipation mode or ring oscillator low power dissipation mode switch the clock source for cpu clock (note 2) low power dissipation mode program write 0 to the fmr01 bit (cpu rewrite mode disabled) set the fmr01 bit by writing 0 and then 1 (cpu rewrite mode enabled) (note 2) jump to a specified address in the flash memory wait until oscillation stabilizes note 1: set the fmr03 bit to 1 after setting the fmr01 bit to 1. note 2: before the clock source for cpu clock can be changed to main clock or sub clock, the clock to which to be changed must be stable. note 3: insert a 15 s wait time in a program. the flash memory cannot be accessed during this wait time.
flash memory 272 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. precautions on cpu rewrite mode described below are the precautions to be observed when rewriting the flash memory in cpu rewrite mode. (1) operation speed before entering cpu rewrite mode (ew0 or ew1 mode), select 10 mhz or less for bclk using the cm06 bit in the cm0 register and the cm17 to cm16 bits in the cm1 register. also, set the pm17 bit in the pm1 register to 1 (with wait state). (2) instructions to prevent from using the following instructions cannot be used in ew0 mode because the flash memorys internal data is referenced: und instruction, into instruction, jmps instruction, jsrs instruction, and brk instruc- tion (3) interrupts ew0 mode ? any interrupt which has a vector in the variable vector table can be used providing that its vector is transferred into the ram area. _______ ? the nmi and watchdog timer interrupts can be used because the fmr0 register and fmr1 regis- ter are initialized when one of those interrupts occurs. the jump addresses for those interrupt service routines should be set in the fixed vector table. _______ because the rewrite operation is halted when a nmi or watchdog timer interrupt occurs, the rewrite program must be executed again after exiting the interrupt service routine. ? the address match interrupt cannot be used because the flash memorys internal data is refer- enced. ew1 mode ? make sure that any interrupt which has a vector in the variable vector table or address match interrupt will not be accepted during the auto program or auto erase period. ? avoid using watchdog timer interrupts. _______ ? the nmi interrupt can be used because the fmr0 register and fmr1 register are initialized when this interrupt occurs. the jump address for the interrupt service routine should be set in the fixed vector table. _______ because the rewrite operation is halted when a nmi interrupt occurs, the rewrite program must be executed again after exiting the interrupt service routine. (4) how to access to set the fmr01, fmr02, or fmr11 bit to 1, write 0 and then 1 in succession. this is necessary to ensure that no interrupts or dma transfers will occur before writing 1 after writing 0. also only _______ when nmi pin is h level. (5) writing in the user rom space ew0 mode ? if the power supply voltage drops while rewriting any block in which the rewrite control program is stored, a problem may occur that the rewrite control program is not correctly rewritten and, conse- quently, the flash memory becomes unable to be rewritten thereafter. in this case, standard serial i/o or parallel i/o mode should be used. ew1 mode ? avoid rewriting any block in which the rewrite control program is stored.
flash memory 273 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. (6) dma transfer in ew1 mode, make sure that no dma transfers will occur while the fmr0 registers fmr00 bit = 0 (during the auto program or auto erase period). (7) writing command and data write the command code and data at even addresses. (8) wait mode when shifting to wait mode, set the fmr01 bit to 0 (cpu rewrite mode disabled) before executing the wait instruction. (9) stop mode when shifting to stop mode, the following settings are required: ? set the fmr01 bit to 0 (cpu rewrite mode disabled) and disable dma transfers before setting the cm10 bit to 1 (stop mode). ? execute the jmp.b instruction subsequent to the instruction which sets the cm10 bit to 1 (stop mode) example program bset 0, cm1 ; stop mode jmp.b l1 l1: program after returning from stop mode (10) low power dissipation mode and ring oscillator low power dissipation mode if the cm05 bit is set to 1 (main clock stop), the following commands must not be executed. ? program ? block erase ? erase all unlocked blocks ? lock bit program
flash memory 274 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. software commands software commands are described below. the command code and data must be read and written in 16- bit units, to and from even addresses in the user rom area. when writing command code, the 8 high- order bits (d 1t Cd 8 ) are ignored. table 1.27.4. software commands read array command (ff 16 ) this command reads the flash memory. writing xxff 16 in the first bus cycle places the microcomputer in read array mode. enter the read address in the next or subsequent bus cycles, and the content of the specified address can be read in 16-bit units. because the microcomputer remains in read array mode until another command is written, the con- tents of multiple addresses can be read in succession. read status register command (70 16 ) this command reads the status register. write xx70 16 in the first bus cycle, and the status register can be read in the second bus cycle. (refer to status register.) when reading the status register too, specify an even address in the user rom area. do not execute this command in ew1 mode. command program clear status register read array read status register (note) first bus cycle second bus cycle lock bit program erase all unlocked block block erase read lock bit status write write write write write write write write mode read write write write write write mode x ba x wa ba ba address srd xxd0 16 xxd0 16 wd xxd0 16 xxd0 16 data (d 0 to d 7 ) xxff 16 xx70 16 xx50 16 xx40 16 xx77 16 xxa7 16 xx20 16 xx71 16 data (d 0 to d 7 ) x x x wa ba x x x address note: it is only blocks 0 to 12 that can be erased by the erase all unlocked block command. block a cannot be erased. use the block erase command to erase block a. srd: status register data (d 7 to d 0 ) wa: write address (make sure the address value specified in the the first bus cycle is the same even address as the write address specified in the second bus cycle.) wd: write data (16 bits) ba: uppermost block address (even address, however) x: any even address in the user rom area x: high-order 8 bits of command code (ignored)
flash memory 275 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. start program completed yes no note: write the command code and data at even number. write the command code xx40 16 to the write address write data to the write address fmr00=1? full status check figure 1.27.8. program command clear status register command (50 16 ) this command clears the status register to 0. write xx50 16 in the first bus cycle, and the fmr06 to fmr07 bits in the fmr0 register and sr4 to sr5 in the status register will be cleared to 0. program command (40 16 ) this command writes data to the flash memory in 1 word (2 byte) units. write xx40 16 in the first bus cycle and write data to the write address in the second bus cycle, and an auto program operation (data program and verify) will start. make sure the address value specified in the first bus cycle is the same even address as the write address specified in the second bus cycle. check the fmr00 bit in the fmr0 register to see if auto programming has finished. the fmr00 bit is 0 during auto programming and set to 1 when auto programming is completed. check the fmr06 bit in the fmr0 register after auto programming has finished, and the result of auto programming can be known. (refer to full status check.) each block can be protected against programming by a lock bit. (refer to data protect function.) writing over already programmed addresses is inhibited. in ew1 mode, do not execute this command on any address at which the rewrite control program is located. in ew0 mode, the microcomputer goes to read status register mode at the same time auto program- ming starts, making it possible to read the status register. the status register bit 7 (sr7) is cleared to 0 at the same time auto programming starts, and set back to 1 when auto programming finishes. in this case, the microcomputer remains in read status register mode until a read command is written next. the result of auto programming can be known by reading the status register after auto program- ming has finished.
flash memory 276 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. write xxd0 16 to the uppermost block address start block erase completed yes no note: write the command code and data at even number. write the command code xx20 16 fmr00=1? full status check figure 1.27.9. block erase command block erase write xx20 16 in the first bus cycle and write xxd0 16 to the uppermost address of a block (even address, however) in the second bus cycle, and an auto erase operation (erase and verify) will start. check the fmr0 registers fmr00 bit to see if auto erasing has finished. the fmr00 bit is 0 during auto erasing and set to 1 when auto erasiing is completed. check the fmr0 registers fmr07 bit after auto erasing has finished, and the result of auto erasing can be known. (refer to full status check.) figure 1.27.9 shows an example of a block erase flowchart. each block can be protected against erasing by a lock bit. (refer to data protect function.) writing over already programmed addresses is inhibited. in ew1 mode, do not execute this command on any address at which the rewrite control program is located. in ew0 mode, the microcomputer goes to read status register mode at the same time auto erasing starts, making it possible to read the status register. the status register bit 7 (sr7) is cleared to 0 at the same time auto erasing starts, and set back to 1 when auto erasing finishes. in this case, the microcomputer remains in read status register mode until the read array or read lock bit status command is written next.
flash memory 277 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. write xxd0 16 to the uppermost block address start lock bit program completed yes no note: write the command code and data at even number. write command code xx77 16 to the uppermost block address fmr00=1? full status check erase all unlocked block write xxa7 16 in the first bus cycle and write xxd0 16 in the second bus cycle, and all blocks except block a will be erased successively, one block at a time. check the fmr0 registers fmr00 bit to see if auto erasing has finished. the result of the auto erase operation can be known by inspecting the fmr0 registers fmr07 bit. each block can be protected against erasing by a lock bit. (refer to data protect function.) in ew1 mode, do not execute this command when the lock bit for any block = 1 (unlocked) in which the rewrite control program is stored, or when the fmr0 registers fmr02 bit = 1 (lock bit disabled). in ew0 mode, the microcomputer goes to read status register mode at the same time auto erasing starts, making it possible to read the status register. the status register bit 7 (sr7) is cleared to 0 at the same time auto erasing starts, and set back to 1 when auto erasing finishes. in this case, the microcomputer remains in read status register mode until the read array or read lock bit status command is written next. note that only blocks 0 to 12 can be erased by the erase all unlocked block command. block a cannot be erased. use the block erase command to erase block a. lock bit program command (77 16 /d0 16 ) this command sets the lock bit for a specified block to 0 (locked). write xx77 16 in the first bus cycle and write xxd0 16 to the uppermost address of a block (even address, however) in the second bus cycle, and the lock bit for the specified block is cleared to 0. make sure the address value specified in the first bus cycle is the same uppermost block address that is specified in the second bus cycle. figure 1.27.10 shows an example of a lock bit program flowchart. the lock bit status (lock bit data) can be read using the read lock bit status command. check the fmr0 registers fmr00 bit to see if writing has finished. for details about the lock bit function, and on how to set the lock bit to 1, refer to data protect function. figure 1.27.10. lock bit program command
flash memory 278 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. blocks not locked write xxd0 16 to the uppermost block address start block locked yes no note: write the command code and data at even number. write the command code xx71 16 fmr00=1? yes no fmr16=0? read lock bit status command (71 16 ) this command reads the lock bit status of a specified block. write xx71 16 in the first bus cycle and write xxd0 16 to the uppermost address of a block (even address, however) in the second bus cycle, and the lock bit status of the specified block is stored in the fmr1 registers fmr16 bit. read the fmr16 bit after the fmr0 registers fmr00 bit is set to 1 (ready). figure 1.27.11 shows an example of a read lock bit status flowchart. figure 1.27.11. read lock bit status command
flash memory 279 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. data protect function each block in the flash memory has a nonvolatile lock bit. the lock bit is effective when the fmr02 bit = 0 (lock bit enabled). the lock bit allows each block to be individually protected (locked) against program- ming and erasure. this helps to prevent data from inadvertently written to or erased from the flash memory. the following shows the relationship between the lock bit and the block status. ? when the lock bit = 0, the block is locked (protected against programming and erasure). ? when the lock bit = 1, the block is not locked (can be programmed or erased. the lock bit is cleared to 0 (locked) by executing the lock bit program command, and is set to 1 (unlocked) by erasing the block. the lock bit cannot be set to 1 by a command. the lock bit status can be read using the read lock bit status command the lock bit function is disabled by setting the fmr02 bit to 1, with all blocks placed in an unlocked state. (the lock bit data itself does not change state.) setting the fmr02 bit to 0 enables the lock bit function (lock bit data retained). if the block erase or erase all unlocked block command is executed while the fmr02 bit = 1, the target block or all blocks are erased irrespective of how the lock bit is set. the lock bit for each block is set to 1 after completion of erasure. for details about the commands, refer to software commands. status register the status register indicates the operating status of the flash memory and whether an erase or program- ming operation terminated normally or in error. the status of the status register can be known by reading the fmr0 registers fmr00, fmr06, and fmr07 bits. table 1.27.5 shows the status register. in ew0 mode, the status register can be read in the following cases: (1) when a given even address in the user rom area is read after writing the read status register command (2) when a given even address in the user rom area is read after executing the program, block erase, erase all unlocked block, or lock bit program command but before executing the read array command. sequencer status (sr7 and fmr00 bits ) the sequence status indicates the operating status of the flash memory. sr7 = 0 (busy) during auto programming, auto erase, and lock bit write, and is set to 1 (ready) at the same time the operation finishes. erase status (sr5 and fmr07 bits) refer to full status check. program status (sr4 and fmr06 bits) refer to full status check.
flash memory 280 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. status register bit sr4 (d 4 ) sr5 (d 5 ) sr7 (d 7 ) sr6 (d 6 ) status name contents sr1 (d 1 ) sr2 (d 2 ) sr3 (d 3 ) sr0 (d 0 ) program status erase status sequencer status reserved reserved reserved reserved "1" ready terminated in error terminated in error - - - - - "0" busy terminated normally terminated normally - - - - - reserved fmr0 register bit fmr00 fmr07 fmr06 value after reset 1 0 0 table 1.27.5. status register ? d 0 to d 7 : indicates the data bus which is read out when the read status register command is executed. ? the fmr07 bit (sr5) and fmr06 bit (sr4) are cleared to 0 by executing the clear status register command. ? when the fmr07 bit (sr5) or fmr06 bit (sr4) = 1, the program, block erase, erase all unlocked block, and lock bit program commands are not accepted.
flash memory 281 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. full status check when an error occurs, the fmr0 registers fmr06 to fmr07 bits are set to 1, indicating occurrence of each specific error. therefore, execution results can be verified by checking these status bits (full status check). table 1.27.6 lists errors and fmr0 register status. figure 1.27.12 shows a full status check flowchart and the action to be taken when each error occurs. table 1.27.6. errors and fmr0 register status frm00 register (status register) status error error occurance condition fmr07 fmr06 (sr5) (sr4) 1 1 command ? when any command is not written correctly sequence error ? when invalid data was written other than those that can be writ- ten in the second bus cycle of the lock bit program, block erase, or erase all unlocked block command (i.e., other than xxd0 16 or xxff 16 ) (note 1) 1 0 erase error ? when the block erase command was executed on locked blocks (note 2) ? when the block erase or erase all unlocked block command was executed on unlocked blocks but the blocks were not auto- matically erased correctly 0 1 program error ? when the block erase command was executed on locked blocks (note 2) ? when the program command was executed on unlocked blocks but the blocks were not automatically programmed correctly. ? when the lock bit program command was executed but not pro- grammed correctly
flash memory 282 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. full status check fmr06 =1 and fmr07=1? no command sequence error yes fmr07= 0? yes erase error no (1) execute the clear status register command to clear these status flags to 0. (2) reexecute the command after checking that it is entered correctly. (1) execute the clear status register command to clear the erase status flag to 0. (2) execute the read lock bit status command to see if the lock bit for the block in error is 0. if so, set the fmr0 registers fmr02 bit to 1. (3) reexecute the block erase or erase all unlocked block command. note 4: if fmr06 or fmr07 = 1, any of the program, block erase, erase all unlocked block, lock bit program, or read lock bit status command is not accepted. execute the clear status register command before executing those commands. fmr06= 0? yes program error no full status check completed note 1: if the error still occurs, the block in error cannot be used. furthermore, if the lock bit = 1 in (2) above, the block in error cannot be used either. (1) execute the clear status register command to clear the erase status flag to 0. (2) execute the read lock bit status command to see if the lock bit for the block in error is 0. if so, set the fmr0 registers fmr02 bit to 1. (3) reexecute the program command. note 2: if the error still occurs, the block in error cannot be used. furthermore, if the lock bit = 1 in (2) above, the block in error cannot be used either. [during programming] (1) execute the clear status register command to clear the erase status flag to 0. (2) set the fmr0 registers fmr02 bit to 1. (3) execute the block erase command to erase the block in error. (4) reexecute the lock bit command. note 3: if the error still occurs, the block in error cannot be used. [during lock bit programming] figure 1.27.12. full status check and handling procedure for each error
flash memory 283 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. standard serial i/o mode in standard serial input/output mode, the user rom area can be rewritten while the microcomputer is mounted on-board by using a serial programmer suitable for the m16c/62p group. for more information about serial programmers, contact the manufacturer of your serial programmer. for details on how to use, refer to the users manual included with your serial programmer. table 1.27.7 lists pin functions (flash memory standard serial input/output mode). figures 1.27.13 to 1.27.15 show pin connections for serial input/output mode. id code check function this function determines whether the id codes sent from the serial programmer and those written in the flash memory match. (refer to the desctiption of the functions to inhibit rewriting flash memory version.)
flash memory 284 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. pin description v cc ,v ss apply the voltage guaranteed for program and erase to vcc pin and 0 v to vss pin. cnv ss connect to vcc pin. reset x in connect a ceramic resonator or crystal oscillator between x in and x out pins. to input an externally generated clock, input it to x in pin and open x out pin. x out byte connect this pin to vcc or vss. av cc , av ss v ref connect avss to vss and avcc to vcc, respectively. enter the reference voltage for ad from this pin. p0 0 to p0 7 input "h" or "l" level signal or open. p1 0 to p1 7 input "h" or "l" level signal or open. p2 0 to p2 7 input "h" or "l" level signal or open. p3 0 to p3 7 input "h" or "l" level signal or open. p4 0 to p4 7 input "h" or "l" level signal or open. p5 1 to p5 4, p5 6, p5 7 input "h" or "l" level signal or open. p5 0 input "h" level signal. p5 5 input "l" level signal. p6 0 to p6 3 input "h" or "l" level signal or open. p6 4 standard serial i/o mode 1: busy signal output pin standard serial i/o mode 2: monitors the boot program operation check signal output pin. p6 5 p6 6 serial data input pin p6 7 serial data output pin p7 0 to p7 7 input "h" or "l" level signal or open. p8 0 to p8 4 , p8 6 , p8 7 input "h" or "l" level signal or open. p9 0 to p9 7 input "h" or "l" level signal or open. p10 0 to p10 7 input "h" or "l" level signal or open. name power input cnv ss reset input clock input clock output byte analog power supply input reference voltage input input port p0 input port p1 input port p2 input port p3 input port p4 input port p5 ce input epm input input port p6 busy output sclk input rxd input txd output input port p7 input port p8 input port p9 input port p10 i/o i i i o i i i i i i i i i i i o i i o i i i i p8 5 nmi input i connect this pin to vcc. standard serial i/o mode 1: serial clock input pin standard serial i/o mode 2: input "l". p12 0 to p12 7 input "h" or "l" level signal or open. p13 0 to p13 7 input "h" or "l" level signal or open. input port p12 input port p13 i i p11 0 to p11 7 input port p11 i input "h" or "l" level signal or open. p14 0 to p14 7 input "h" or "l" level signal or open. input port p14 i reset input pin. while reset pin is "l" level, input a 20 cycle or longer clock to x in pin. (note 1) (note 2) (note 2) (note 2) (note 2) (note 2) (note 2) table 1.27.7. pin functions (flash memory standard serial i/o mode) ___________ note 1: when using standard serial input/output mode 1, the txd pin must be held high while the reset pin is pulled low. therefore, connect this pin to v cc via a resistor. because this pin is directed for data output after reset, adjust the pull-up resistance value in the system so that data transfers will not be affected. note 2: available in only the 128-pin version.
flash memory 285 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.27.13. pin connections for serial i/o mode (1) vcc vss rxd txd sclk cnvss ce epm busy reset 1 2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 5354 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 1 00 connect oscillator circuit. cnvss vcc epm vss reset vss to vcc ce vcc signal value mode setup method package: 100p6s-a m16c/62p group (flash memory version)
flash memory 286 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.27.14. pin connections for serial i/o mode (2) cnv ss reset v ss v cc ce busy epm sclk r x d t x d 1 23 45 678910111213141516171819202122232425 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51525354555657585960616263646566676869707172737475 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 10 0 cnvss vcc epm vss reset vss to vcc ce vcc signal value mode setup method connect oscillator circuit. package: 100p6q-a m16c/62p group (flash memory version)
flash memory 287 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. figure 1.27.15. pin connections for serial i/o mode (3) package: 128p6q-a 1 2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930 73 74 75 7677 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101102 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 104 105 106 107 108 31 32 33 34 35 36 37 66 67 68 69 70 71 72 38 65 64 103 vcc ce epm vss cnvss reset sclk busy rxd txd cnvss vcc epm vss reset vss to vcc ce vcc signal valu e mode setup method connect oscillator circuit. m16c/62p group (flash memory version)
flash memory 288 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. example of circuit application in the standard serial i/o mode figure 1.27.16 and 1.27.17 show example of circuit application in standard serial i/o mode 1 and mode 2, respectively. refer to the user's manual for serial writer to handle pins controlled by a serial writer. figure 1.27.16. circuit application in standard serial i/o mode 1 clock input busy output data input data output busy sclk t x d cnvss p5 0 (ce) p5 5 (epm) nmi reset rxd reset input user reset singnal microcomputer (1) control pins and external circuitry will vary according to programmer. for more information, see the programmer manual. (2) in this example, modes are switched between single-chip mode and standard serial input/output mode by controlling the cnvss input with a switch. (3) if in standard serial input/output mode 1 there is a possibility that the user reset signal will go low during serial input/output mode, break the connection between the user reset signal and reset pin by using, for example, a jumper switch. m16c/62p group (flash memory version)
flash memory 289 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. monitor output data input data output busy sclk txd cnvss p5 0 (ce) p5 5 (epm) nmi rxd microcomputer (1) in this example, modes are switched between single-chip mode and standard serial input/output mode by controlling the cnvss input with a switch. figure 1.27.17. circuit application in standard serial i/o mode 2
flash memory 290 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. parallel i/o mode in parallel input/output mode, the user rom and boot rom areas can be rewritten by using a parallel programmer suitable for the m16c/62p group. for more information about parallel programmers, contact the manufacturer of your parallel programmer. for details on how to use, refer to the users manual in- cluded with your parallel programmer. user rom and boot rom areas in the boot rom area, an erase block operation is applied to only one 4 kbyte block. the boot rom area contains a standard serial input/output mode based rewrite control program which was written in it when shipped from the factory. therefore, when using a serial programmer, be careful not to rewrite the boot rom area. when in parallel output mode, the boot rom area is located at addresses 0ff000 16 to 0fffff 16 . when rewriting the boot rom area, make sure that only this address range is rewritten. (do not access other than the addresses 0ff000 16 to 0fffff 16 .) rom code protect function the rom code protect function inhibits the flash memory from being read or rewritten. (refer to the description of the functions to inhibit rewriting flash memory version.)
291 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r package outline under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. package outline qfp100-p-1420-0.65 1.58 weight(g) C jedec code eiaj package code lead material alloy 42 100p6s-a plastic 100pin 14 ? 20mm body qfp C 0.1 C CC 0.2 C C CC C C CC C symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.35 CC i 2 1.3 CC m d 14.6 CC m e 20.6 10 0 0.1 1.4 0.80.60.4 23.122.822.5 17.116.816.5 0.65 20.220.019.8 14.214.013.8 0.20.150.13 0.40.30.25 2.8 0 3.05 e e e e c h e 1 30 31 81 50 80 51 h d d m d m e a f a 1 a 2 l 1 l y b 2 i 2 recommended mount pad detail f 100 x C C 0.13 b x m mmp lqfp100-p-1414-0.50 weight(g) C 0.63 jedec code eiaj package code lead material cu alloy 100p6q-a plastic 100pin 14 ? 14mm body lqfp C 0.1 C CC 0.2 C C CC C C CC C symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.225 CC i 2 0.9 CC m d 14.4 CC m e 14.4 10 0 0.1 1.0 0.70.50.3 16.216.015.8 16.216.015.8 0.5 14.114.013.9 14.114.013.9 0.1750.1250.105 0.280.180.13 1.4 0 1.7 e e e h e 1 76 75 51 50 26 25 h d d a f y 100 lp 0.45 C C 0.6 0.25 C 0.75 C 0.08 x a3 b x m a 1 a 2 l 1 l detail f lp a3 c m d l 2 b 2 m e e recommended mount pad mmp
292 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r package outline under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. m d l 2 b 2 m e e recommended mount pad lp 0.45 C C 0.6 0.25 C 0.75 C 0.08 x a3 y b x m lp a3 lqfp128-p-1420-0.50 C weight(g) C jedec code eiaj package code lead material cu alloy 128p6q-a plastic 128pin 14 ? 20mm body lqfp 1.5 0.125 1.4 CC 0.2 C C CC C C CC C symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.225 C 1.0 i 2 C CC m d 14.4 CC m e 20.4 8 0 0.1 1.0 0.650.50.35 22.222.021.8 16.216.015.8 0.5 20.120.019.9 14.114.013.9 0.1750.1250.105 0.270.220.17 1.4 0.05 1.7 e e e c h e 1 38 39 64 65 h d d a f a 1 a 2 l 1 l detail f 128 103 102 mmp
293 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r differences between m16c/62p and m16c/62a under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. differences between m16c/62p and m16c/62a item m16c/62a m16c/62p shortest instruction execution time supply voltage 62.5ns (f(x in )=16mh z , v cc =4.2v to 5.5v) 100ns (f(x in )=10mh z , v cc =2.7v to 5.5v with software one-wait) 4.2v to 5.5v (f(x in )=16mh z , without software wait) 2.7v to 5.5v (f(x in )=10mh z , with software one-wait) 41.7ns (f(bclk)=24mh z , v cc1 =3.0 to 5.5v) 100ns (f(bclk)=10mh z , v cc1 =2.7 to 5.5v) v cc1 =3.0 to 5.5v, v cc2 =3.0v to v cc1 (f(bclk)=24mh z ) v cc1 =v cc2 =2.7 to 5.5v (f(bclk)=10mh z ) clock generating circuit address match interrupt memory area watchdog timer memory area expandable (4 mbytes) x in , x cin main clock division rate when main clock is stopped: no change x in drive capacity when main clock is stopped: no change 2 watchdog timer interrupt or watchdog timer reset is selected count source protective mode is available 32.5ma (v cc =5v, f(x in )=16mhz) 8.5ma (v cc =3v, f(x cin )=10mhz with software one-wait) 0.9 a(v cc =3v, f(x cin )=32khz, when wait mode) low power consumption 1 mbytes fixed pll, x in , x cin , ring oscillator main clock division rate when main clock is stopped: divide-by-8 frequency x in drive capacity when main clock is stopped: high 4 watchdog timer interrupt no count source protective mode 18ma (v cc1 =v cc2 =5v, f(bclk)=24mhz) 8ma (v cc1 =v cc2 =3v, f(bclk)=10mhz) 1.8 a(v cc1 =v cc2 =3v, f(x cin )=32khz, when wait mode) note: about the details and the electric characteristics, refer to data sheet. differences in mask rom version and flash memory version (1) (note) i/o power supply double (v cc1 , v cc2 ) single (v cc ) package 100-pin, 128-pin plastic mold qfp 80-pin, 100-pin plastic mold qfp oscillation stop, re-oscillation detection function built-in none external device connect area 04000 16 C07fff 16 (pm13=0) 08000 16 C0ffff 16 (pm10=0) 10000 16 C26fff 16 28000 16 C7ffff 16 80000 16 Ccffff 16 (pm13=0) d0000 16 Cfffff 16 (microprocessor mode) 04000 16 C05fff 16 (pm13=0) 06000 16 Ccffff 16 d0000 16 Cfffff 16 (microprocessor mode) upper address in memory expansion mode and microprocessor mode p4 0 to p4 3 (a 16 to a 19 ), p3 4 to p3 7 (a 12 to a 15 ) : switchable between address bus and port p4 0 to p4 3 (a 16 to a 19 ) : switchable between address bus and port access to sfr 1 wait fixed variable (1 to 2 waits) software wait to external area variable (0 to 1 wait) variable (0 to 3 waits) protect can be set for pm0, pm1, cm0, cm1, pd9, s3c, s4c registers can be set for pm0, pm1, pm2, cm0, cm1, cm2, plc0, invc0, invc1, pd9, s3 c, s4c, tb2sc, pclkr, vcr2, d4int registers voltage detection circuit built-in vdet2, vdet3, vdet4 detect power supply voltage down detect interrupt hardware reset 2 none system clock protective function built-in none (protected by protect register)
294 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r differences between m16c/62p and m16c/62a under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. item m16c/62a m16c/62p serial i/o (uart0 to uart2) (uart, clock synchronous,) x 2 (uart, clock synchronous, iic bus, ie bus) x 1 (uart, clock synchronous, i 2 c bus, ie bus) x 3 differences in mask rom version and flash memory version (2) (note) timers a, b count source selectable: f 1 , f 8 , f 32 , f c32 selectable: f 1 , f 2 , f 8 , f 32 , f c32 timer functions for three-phase motor control timer a two-phase pulse signal processing no z-phase (counter reset input z-phase (counter reset) input is available no function protect by protect register count source is selectable: f 1, f 8, f 32, f c32 dead time timer count source is fixed at f 1 /2 function protect by protect register count source is selectable: f 1, f 2, f 8, f 32, f c32 dead time timer count source is selectable: f 1, f 1 divided by 2, f 2 , f 2 divided by 2 output polarity is selectable carrier wave phase detectable three-phase output port nmi control uart0 to uart2, si/o3, si/o4 count source selectable: f 1 , f 8 , f 32 selectable: f 1sio , f 2sio , f 8sio , f 32sio serial i/o sleep function a-d converter si/o3, si/o4 clock polarity selection 10 bits x 8 channels expandable up to 10 channels selectable have analog or digital delay is selected as sda delay sda digital delay count source: 1/ f(x in ) serial i/o i 2 c mode sda delay not selectable none 10 bits x 8 channels expandable up to 26 channels only digital delay is selected as sda delay sda digital delay count source: brg note: about the details and the electric characteristics, refer to data sheet. uart2 data transmit timing after data was written, transfer starts at the 2nd brg overflow timing (same as uart0 and uart1) after data was written, transfer starts at the 1st brg overflow timing (output starts one cycle of brg overflow earlier than uart0 and uart1) serial i/o i 2 c mode start condition, stop condition: auto-generationable start condition, stop condition: not auto-generationable a-d converter operation clock selectable: f ad , f ad /2, f ad /4 selectable: f ad , f ad divided by 2, 3, 4, 6, 12 a-d converter input pin fixed at port p10 selectable: ports p0, p2, p10 assert low when receive buffer is read assert low when reception is completed serial i/o rts timing cts/rts separate function none have
295 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r differences between m16c/62p and m16c/62a under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. item m16c/62a m16c/62p user rom blocks 7 blocks: 8 kbytes x 2, 16 kbytes x1, 32 kbytes x 1, 64 kbytes x 3 (flash memory: max. 256 kbytes) 14 blocks: 4 kbytes x 3, 8 kbytes x 3, 32 kbytes x1, 64 kbytes x 7 (flash memory: max. 512 kbytes) block status after program function none have note: about the details and the electric characteristics, refer to data sheet. differences in flash memory version(note) program command (software command) page program command: none program command: have (program method: in units of word, in units of byte) page program command: have program command: none (program method: in units of page) program manner page word cpu rewrite mode no ew1 mode ew1 mode is available
296 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r register index under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. register index a ad0 to ad7 192 adcon0 191 adcon1 191 adcon2 192 aier 92 aier2 92 c cm0 53 cm1 54 cm2 55 cpsrf 111 , 124 crcd 208 crcin 208 cse 40 csr 34 d d4int 25 da0 207 da1 207 dacon 207 dar0 101 dar1 101 dbr 44 dm0con 100 dm1con 100 dm1sl 100 dtt 133 f fidr 268 fmr0 268 i ictb2 134 idb0 133 idb1 133 ifsr 89 ifsr2a 89 invc0 131 invc1 132 o onsf 111 p p0 to p13 217 pc14 218 pclkr 56 pcr 220 pd0 to pd13 216 plc0 57 pm0 30 pm1 31 pm2 56 prcr 74 pur0 to pur2 219 pur3 218 r rmad0 to rmad3 92 romcp 264 s s3brg 185 s3c 185 s3trr 185 s4brg 185 s4c 185 s4trr 185 sar0 101 sar1 101 t ta0 to ta4 110 ta0mr to ta4mr 109 ta1 134 ta11 134 ta1mr 136 ta2 134 ta21 134
297 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r register index under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. ta2mr 136 ta4 134 ta41 134 ta4mr 136 tabsr 110 , 124 , 135 tb0 to tb5 124 tb0mr to tb5mr 123 tb2 135 tb2mr 136 tb2sc 134 tbsr 124 tcr0 101 tcr1 101 trgsr 111 , 135 u u0brg to u2brg 142 u0c0 to u2c0 143 u0c1 to u2c1 144 u0mr to u2mr 143 u0rb to u2rb 142 u0smr to u2smr 145 u0smr2 to u2smr2 146 u0smr3 to u2smr3 146 u0smr4 to u2smr4 147 u0tb to u2tb 142 ucon 145 udf 110 v vcr1 25 vcr2 25 w wdc 24 , 96 wdts 96
revision history m16c/62p group data sheet rev. date description page summary 298 1.0 jan/31/y03 (continued) applications are partly revised. table 1.1.1 is partly revised. table 1.1.3 is partly revised. figure 1.1.2 is partly revised. explanation of memory is partly revised. explanation of hardware reset 1 is partly revised. figure 1.5.1 is partly revised. figure 1.5.2 is partly revised. figure 1.5.4 is partly revised. vcr2 register in figure 1.5.6 is partly revised. figure 1.5.6 is partly revised. explanation of power supply down detection interrupt is partly revised. figure 1.6.1 is partly revised. figure 1.6.2 is partly revised. table 1.7.5 is partly revised. table 1.7.7 is partly revised. figure 1.7.8 is partly revised. explanation of 4 mbyte mode is partly revised. notes 12 and 13 in figure 1.9.2 is partly revised. notes 2 and 5 in figure 1.9.3 is partly revised. figure 1.9.4 is partly revised. note 4 in figure 1.9.6 is partly revised. explanation of pll clock is partly revised. figure 1.9.9 is partly revised. explanation of cpu clock and bclk is partly revised. explanation of low-speed mode is partly revised. explanation of low power dissipation mode is partly revised. explanation of ring oscillator low power dissipation mode is partly revised. table 1.9.3 is partly revised. table 1.9.5 is partly revised. figure 1.9.10 is partly revised. figure 1.9.11 is partly revised. table 1.9.7 is added. explanation of system clock protective function is partly revised. explanation of power supply down detection interrupt is partly revised. table 1.11.1 is partly revised. figure 1.11.9 is partly revised. wdts register in figure 1.12.2 is partly revised. figure 1.13.2 is partly revised. figure 1.13.3 is partly revised. figure 1.13.5 is partly revised. table 1.13.3 is partly revised. explanation of dma enable is partly revised. figure 1.14.3 is partly revised. table 1.14.3 is partly revised. explanation of counter initialization by two-phase pulse signal processing is partly revised. figure 1.14.10 is partly revised. figure 1.14.14 is partly revised. figure 1.14.15 is partly revised. 1 2 5 5 11 20 21 22 24 25 26 27 30 31 39 41 43 44 53 54 55 57 60 61 62 63 63 64 64 65 68 69 70 71 77 78 88 96 99 100 103 104 105 109 115 117 117 122 122
revision history m16c/62p group data sheet rev. date description page summary 299 figure 1.15.3 is partly revised. figure 1.15.7 is partly revised. figure 1.15.8 is partly revised. figure 1.16.1 is partly revised. figure 1.16.3 is partly revised. note 7 is added to tai, tai1 register in figure 1.16.5. figure 1.16.8 is partly revised. uismr2 register in figure 1.17.7 is partly revised. figure 1.20.1 is partly revised. table 1.20.2 and table 1.20.3 are partly revised. figure 1.20.4 is partly revised. explanation of arbitration is partly revised. explanation of transfer clock is partly revised. explanation of ack and nack is partly revised. explanation of special mode 4 (sim mode) is partly revised. table 1.20.9 is partly revised. figure 1.21.1 is partly revised. figure 1.21.4 is partly revised. explanation of external operation amp connection mode is partly revised. explanation of caution of using a-d converter is partly revised. figure 1.22.11 is partly revised table 1.23.1 is partly revised. figure 1.23.3 is partly revised. figure 1.25.9 is partly revised. table 1.26.1 is partly revised. table 1.26.2 is partly revised. note 1 of table 1.26.3 is partly revised. note 1 of table 1.26.4 is partly revised. table 1.26.6 is partly revised. note 1 of table 1.26.9 is partly revised. note 1 of table 1.26.10 is partly revised. measurement conditions of timing requirements are partly revised. table 1.26.11 is partly revised. measurement conditions of timing requirements are partly revised. table 1.26.18 is added. measurement conditions of timing requirements are partly revised. measurement conditions of switching characteristics are partly revised. measurement conditions of switching characteristics are partly revised. measurement conditions of switching characteristics are partly revised. figure 1.26.2 is partly revised. figure 1.26.9 is partly revised. note of table 1.26.28 is partly revised. figure 1.26.29 is partly revised. measurement conditions of timing requirements are partly revised. table 1.26.30 is partly revised. measurement conditions of timing requirements are partly revised. table 1.26.37 is added. measurement conditions of timing requirements are partly revised. measurement conditions of switching characteristics are partly revised. measurement conditions of switching characteristics are partly revised. 124 128 128 130 132 134 137 146 163 164, 165 169 169 170 171 179 179 184 187 203 205 205 206 207 218 223 224 225 225 225 227 228 229 229 230 230 231 232 233 234 235 242 244 245 246 246 247 247 248 249 250 1.0 jan/31/y03 (continued)
revision history m16c/62p group data sheet rev. date description page summary 300 measurement conditions of switching characteristics are partly revised. figure 1.26.12 is partly revised. figure 1.26.15 is partly revised. figure 1.26.16 is partly revised. figure 1.26.17 is partly revised. figure 1.26.18 is partly revised. figure 1.26.19 is partly revised. figure 1.26.20 is partly revised. explanation of memory map is partly revised. explanation of boot mode is partly revised. figure 1.27.3 is partly revised. note of fidr register in figure 1.27.4 is partly revised. figure 1.27.7 is partly revised. explanation of interrupts is partly revised. explanation of writing in the user rom space is partly revised. table 1.27.4 is partly revised. explanation of read array command is partly revised. explanation of program command is partly revised. figure 1.27.15 is partly revised. partly revised. 251 252 255 256 257 258 259 260 262 263 264 268 271 272 272 274 274 278 287 293 1.0 jan/31/y03 (continued)
? 2003 mitsubishi electric corp. printed in japan (rod) ii new publication, effective february 2003. specifications subject to change without notice. notes regarding these materials ? these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product b est suited to the customers application; they do not convey any license under any intellectual property rights, or any other right s, belonging to mitsubishi electric corporation or a third party. ? mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-partys rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materia ls. ? all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by mitsubishi electric corpora tion without notice due to product improvements or other reasons. it is therefore recommended that customers contact mitsubishi elec tric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. mitsubishi electric corporation assu mes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by mitsubishi electric corporation by various means, including the mitsubish i semiconductor home page (http://www.mitsubishichips.com). ? when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. mitsubishi electric corporation assumes no responsibility for any damage, liability or other loss res ulting from the information contained herein. ? mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used und er circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mits ubishi semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. ? the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these m aterials. ? if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is pro hibited. ? please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further details on these materials or the products contained therein. keep safety first in your circuit designs! ? mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or prope rty damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
mit su bi s hi 1 6 -bit s in g le- c hip mi c r oco mp u te r m1 6c family / m1 6c/60 s erie s u sa g e n otes r e f erence b oo k m16c/62 (m16c/62p) group before using this material, please visit the above website to confirm that this is the most current document available. http://www.infomicom.maec.co.jp/indexe.htm revision date: february 14, 2003
keep safety first in your circuit designs! notes regarding these materials ? mitsubishi electric corporation puts the maximum effort into making semiconductor prod- ucts better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with ap- propriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non- flammable material or (iii) prevention against any malfunction or mishap. ? these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. ? mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. ? all information contained in these materials, including product data, diagrams, charts, pro- grams and algorithms represents information on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. mitsubishi electric corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by mitsubishi electric corporation by various means, including the mitsubishi semiconductor home page (http:// www.mitsubishichips.com). ? when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all informa- tion as a total system before making a final decision on the applicability of the information and products. mitsubishi electric corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. ? mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semicon- ductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. ? the prior written approval of mitsubishi electric corporation is necessary to reprint or repro- duce in whole or in part these materials. ? if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be im- ported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/ or the country of destination is prohibited. ? please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further details on these materials or the products contained therein.
preface this book describes the m16c/62 (m16c/62p) group's precautions for use, which contains paragraphs describing pre- cautions of the user's manual and technical news relevant to these paragraphs. please refer to this book when developing your systems. however, all of precautions are not contained in this book, please perform sufficient evaluation under systems development.
1 1.1 precautions for interrupts mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. 1. usage precaution 1.1 precautions for interrupts 1.1.1 reading address 00000 16 do not read the address 00000 16 in a program. when a maskable interrupt request is accepted, the cpu reads interrupt information (interrupt number and interrupt request priority level) from the address 00000 16 during the interrupt sequence. at this time, the ir bit for the accepted interrupt is cleared to 0. if the address 00000 16 is read in a program, the ir bit for the interrupt which has the highest priority among the enabled interrupts is cleared to 0. this causes a problem that the interrupt is canceled, or an unexpected interrupt is generated.
2 1.1 precautions for interrupts mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. 1.1.2 setting the sp set any value in the sp before accepting an interrupt. the sp is cleared to 0000 16 after reset. therefore, if an interrupt is accepted before setting any value in the sp, the program may go out of control. _______ especially when using nmi interrupt, set a value in the sp at the beginning of the program. for the first _______ and only the first instruction after reset, all interrupts including nmi interrupt are disabled.
3 1.1 precautions for interrupts mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. _______ 1.1.3 the nmi interrupt _______ _______ 1. the nmi interrupt cannot be disabled. if this interrupt is unused, connect the nmi pin to v cc via a resistor (pull-up). _______ 2. the input level of the nmi pin can be read by accessing the p8 register s p8_5 bit. note that the p8_5 _______ bit can only be read when determining the pin level after an nmi interrupt is generated. _______ 3. stop mode cannot be entered into while input on the nmi pin is low. this is because while input on the _______ nmi pin is low the cm1 register s cm10 bit is fixed to 0 . _______ _______ 4. do not go to wait mode while input on the nmi pin is low. this is because when input on the nmi pin goes low, the cpu stops but cpu clock remains active; therefore, the current consumption in the chip does not drop. in this case, normal condition is restored by an interrupt generated thereafter. _______ 5. the low and high level durations of the input signal to the nmi pin must each be 2 cpu clock cycles + 300 ns or more.
4 1.1 precautions for interrupts mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. ______ figure 1.1.1. procedure for changing the int interrupt generate factor set the ilvl2 to ilvl0 bits to '000 2 ' (= level 0) (disable int interrupt) set the pol bit set the ilvl2 to ilvl0 bits to '001 2 ' (=level 1) to '111 2 ' (=level 7) (enable the accepting of int interrupt request) set the i flag to 0 (=disable interrupt) set the i flag to 1 (= enable interrupt) note: execute the setting above individually. do not execute two or more settings at once (by one instruction). set the ir bit to 0 (=interrupt not requested) ______ 1.1.4 int interrupt ________ 1. either an l level or an h level of at least 250 ns width is necessary for the signal input to pins int 0 ________ through int 5 regardless of the cpu operation clock. ________ ________ 2. when the polarity of the int 0 to int 5 pins is changed or the interrupt request cause of the software interrupt numbers 8 to 9 is changed, the ir bit is sometimes set to 1 (interrupt request). after these changes were made, set the interrupt request bit to 0 (no interrupt request). figure 1.1.1 shows the ______ procedure for changing the int interrupt generate factor.
5 1.1 precautions for interrupts mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. 1.1.5 watchdog timer interrupt initialize the watchdog timer after the watchdog timer interrupt occurs.
6 1.1 precautions for interrupts mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. 1.1.6 rewrite the interrupt control register each interrupt control register can only be modified while no interrupt requests corresponding to that register are generated. if interrupt requests managed by any interrupt control register are likely to occur, disable the interrupts before modifying the register. a sample program is shown below. to modify any interrupt control register after disabling interrupts, be careful with the instructions used. (1) modifying other than the ir bit if an interrupt request corresponding to that register is generated while executing the instruction, the ir bit may not be set to 1 (= interrupt requested), with the result that the interrupt request is ignored. if this presents a problem, use the following instructions to modify the register. instructions to use: and, or, bclr, bset (2) modifying the ir bit even when the ir bit is cleared to 0 (= interrupt not requested), it may not actually be cleared to 0 depending on the instruction used. therefore, use the mov instruction to clear the ir bit. example 1: int_switch1: fclr i ; disable interrupts. and.b #00h, 0055h ; set the ta0ic register to 00 16 . nop ; four nop instructions are required when using hold function. nop fset i ; enable interrupts. example 2: int_switch2: fclr i ; disable interrupts. and.b #00h, 0055h ; set the ta0ic register to 00 16 . mov.w mem, r0 ; dummy read. fset i ; enable interrupts. example 3: int_switch3: pushc flg ; push flag register onto stack fclr i ; disable interrupts. and.b #00h, 0055h ; set the ta0ic register to 00 16 . popc flg ; enable interrupts. why the fset i instruction is preceded by two nop instructions (four when using hold function) in example 1 and why the fset i instruction is preceded by a dummy read in example 2 this is to prevent the i flag from being set to 1 before writing to the interrupt control register for reasons of the instruction queue buffer.
1.2 precautions for protect 7 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. 1.2 precautions for protect set the prc2 bit to 1 (write enabled) and then write to any address, and the prc2 bit will be cleared to 0 (write protected). the registers protected by the prc2 bit should be changed in the next instruction after setting the prc2 bit to 1 . make sure no interrupts or dma transfers will occur between the instruction in which the prc2 bit is set to 1 and the next instruction.
8 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r 1.3 precautions for dmac under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. 1.3 precautions for dmac 1.3.1 write to dmae bit in dmicon register when both of the conditions below are met, follow the steps below. conditions ? the dmae bit is set to 1 again while it remains set (dmai is in an active state). ? a dma request may occur simultaneously when the dmae bit is being written. step 1: write 1 to the dmae bit and dmas bit in dmicon register simultaneously (*1) . step 2: make sure that the dmai is in an initial state (*2) in a program. if the dmai is not in an initial state, the above steps should be repeated. notes: *1. the dmas bit remains unchanged even if 1 is written. however, if 0 is written to this bit, it is set to 0 (dma not requested). in order to prevent the dmas bit from being modified to 0 , 1 should be written to the dmas bit when 1 is written to the dmae bit. in this way the state of the dmas bit immediately before being written can be maintained. similarly, when writing to the dmae bit with a read-modify-write instruction, 1 should be written to the dmas bit in order to maintain a dma request which is generated during execution. *2. read the tcri register to verify whether the dmai is in an initial state. if the read value is equal to a value which was written to the tcri register before dma transfer start, the dmai is in an initial state. (if a dma request occurs after writing to the dmae bit, the value written to the tcri register is 1 .) if the read value is a value in the middle of transfer, the dmai is not in an initial state.
1.4 precautions for timers 9 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. 1.4 precautions for timers 1.4.1 timers a and b this section describes precautions for timers a and b. precautions for each mode should be referred as well. 1. after reset, timers stop. after setting mode, count source or counter value, the tais bit (i=0 to 4) or tbjs bit (j=0 to 5) in the tabsr or tbsr register should be set to 1 (starts counting). make sure that the tais bit or tbjs bit is set to 0 (stops counting) before changing the registers and bits listed below. ? taimr register and tbjmr register ? tai register and tbj register ? udf register ? tazie, ta0tgl and ta0tgh bits in onsf register ? trgsr register
1.4 precautions for timers 10 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. 1.4.2 timer a 1.4.2.1 timer a (timer mode) 1. after reset, the tabsr register tais bit (i = 0 to 4) is cleared to 0 (stops counting). select opera- tion mode and set a value in the tai register before setting the tais bit to 1 (starts counting). 2. while counting is in progress, the counter value can be read out at any time by reading the tai register. however, if the counter is read at the same time it is reloaded, the value ffff 16 is read. also, if the counter is read before it starts counting after a value is set in the tai register while not counting, the set value is read. ______ 3. if a low-level signal is applied to the nmi pin when the tb2sc register ivpcr1 bit = 1 (three-phase ______ output forcible cutoff by input on nmi pin enabled), the ta1 out , ta2 out and ta4 out pins go to a high-impedance state.
1.4 precautions for timers 11 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. 1.4.2.2 timer a (event counter mode) 1. after reset, the tabsr register tais bit (i = 0 to 4) is cleared to 0 (stopped counting). select operation mode and set a value in the tai register before setting the tais bit to 1 (start counting). 2. while counting is in progress, the counter value can be read out at any time by reading the tai register. however, ffff 16 can be read in underflow, while reloading, and 0000 16 in overflow. when setting tai register to a value during a counter stop, the setting value can be read before a counter starts counting. also, if the counter is read before it starts counting after a value is set in the tai register while not counting, the set value is read. ______ 3. if a low-level signal is applied to the nmi pin when the tb2sc register ivpcr1 bit = 1 (three-phase ______ output forcible cutoff by input on nmi pin enabled), the ta1 out , ta2 out and ta4 out pins go to a high-impedance state.
1.4 precautions for timers 12 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. 1.4.2.3 timer a (one-shot timer mode) 1. after reset, the tabsr register tais bit (i = 0 to 4) is cleared to 0 (stopped counting). select operation mode and set a value in the tai register before setting the tais bit to 1 (start counting). 2. when setting tabsr register to 0 (count stop), the followings occur: ? a counter stops counting and a content of reload register is reloaded. ? tai out pin outputs l . ? after one cycle of the cpu clock, the ir bit of taiic register is set to 1 (interrupt request). 3. output in one-shot timer mode synchronizes with a count source internally generated. when an external trigger has been selected, one-cycle delay of a count source as maximum occurs between a trigger input to tai in pin and output in one-shot timer mode. 4. the ir bit is set to 1 when timer operation mode is set with any of the following procedures: ? select one-shot timer mode after reset. ? change an operation mode from timer mode to one-shot timer mode. ? change an operation mode from event counter mode to one-shot timer mode. to use the timer ai interrupt (the ir bit), set the ir bit to 0 after the changes listed above have been made. 5. when a trigger occurs, while counting, a counter reloads the reload register to continue counting after generating a re-trigger and counting down once. to generate a trigger while counting, gener- ate a second trigger between occurring the previous trigger and operating longer than one cycle of a timer count source. ______ 6. if a low-level signal is applied to the nmi pin when the tb2sc register ivpcr1 bit = 1 (three-phase ______ output forcible cutoff by input on nmi pin enabled), the ta1 out , ta2 out and ta4 out pins go to a high-impedance state.
1.4 precautions for timers 13 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. 1.4.2.4 timer a (pulse width modulation mode) 1. after reset, the tabsr register tais bit (i = 0 to 4) is cleared to 0 (stopped counting). select operation mode and set a value in the tai register before setting the tais bit to 1 (start counting). 2. the ir bit is set to 1 when setting a timer operation mode with any of the following procedures: ? select the pwm mode after reset. ? change an operation mode from timer mode to pwm mode. ? change an operation mode from event counter mode to pwm mode. to use the timer ai interrupt (interrupt request bit), set the ir bit to 0 by program after the above listed changes have been made. 3. when setting tais register to 0 (count stop) during pwm pulse output, the following action occurs: ? stop counting. ? when tai out pin is output h , output level is set to l and the ir bit is set to 1 . ? when tai out pin is output l , both output level and the ir bit remains unchanged. ______ 4. if a low-level signal is applied to the nmi pin when the tb2sc register ivpcr1 bit = 1 (three-phase ______ output forcible cutoff by input on nmi pin enabled), the ta1 out , ta2 out and ta4 out pins go to a high-impedance state.
1.4 precautions for timers 14 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. 1.4.3 timer b 1.4.3.1 timer b (timer mode and event counter mode) 1. after reset, the tbis bit (i = 0 to 5) is cleared to 0 (stopped counting). select operation mode and set a value in the tbi register before setting the tbis bit to 1 (start counting). the tb0s to tb2s bits are the bits 5 to 7 of tabsr register, the tb3s to tb5s bits are the bits 5 to 7 of tbsr register. 2. a value of a counter, while counting, can be read in tbi register at any time. ffff 16 is read while reloading. setting value is read between setting values in tbi register at count stop and starting a counter.
1.4 precautions for timers 15 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. 1.4.3.2 timer b (pulse period/pulse width measurement mode) 1. the ir bit of tbiic register (i=0 to 5) goes to 1 (overflow), when an effective edge of a measure- ment pulse is input or timer bi is overflowed. the factor of interrupt request can be determined by use of the mr3 bit of tbimr register within the interrupt routine. 2. if the source of interrupt cannot be identified by the mr3 bit such as when the measurement pulse input and a timer overflow occur at the same time, use another timer to count the number of times timer b has overflowed. 3. to set the mr3 bit to 0 (no overflow), set tbimr register with setting the tbis bit to 1 and counting the next count source after setting the mr3 bit to 1 (overflow). 4. use the ir bit of tbiic register to detect only overflows. use the mr3 bit only to determine the interrupt factor within the interrupt routine. 5. when a count is started and the first effective edge is input, an indeterminate value is transferred to the reload register. at this time, timer bi interrupt request is not generated. 6. a value of the counter is indeterminate at the beginning of a count. mr3 may be set to 1 and timer bi interrupt request may be generated between a count start and an effective edge input. 7. when changing the mr1 to mr0 bits of tbimr after a count is started, the ir bit of tbiic register may be set to 1 (interrupt request). note that the ir bit does not change if the same value as before is written to the mr1 to mr0 bits. 8. for pulse width measurement, pulse widths are successively measured. use program to check whether the measurement result is an h level width or an l level width.
1.5 precautions for serial i/o (clock-synchronous serial i/o) 16 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. 1.5 precautions for serial i/o (clock-synchronous serial i/o) 1.5.1 transmission/reception _______ ________ 1. with an external clock selected, and choosing the rts function, the output level of the rtsi pin goes to l when the data-receivable status becomes ready, which informs the transmission side that the ________ reception has become ready. the output level of the rtsi pin goes to h when reception starts. so if ________ ________ the rtsi pin is connected to the ctsi pin on the transmission side, the circuit can transmission and _______ reception data with consistent timing. with the internal clock, the rts function has no effect. _______ 2. if a low-level signal is applied to the nmi pin when the tb2sc register ivpcr1 bit = 1 (three-phase _______ _________ output forcible cutoff by input on nmi pin enabled), the rts 2 and clk 2 pins go to a high-impedance state.
1.5 precautions for serial i/o (clock-synchronous serial i/o) 17 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. 1.5.2 transmission when an external clock is selected, the conditions must be met while if the uic0 register s ckpol bit = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the external clock is in the high state; if the uic0 register s ckpol bit = 1 (transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state. ? the te bit of uic1 register= 1 (transmission enabled) ? the ti bit of uic1 register = 0 (data present in uitb register) _______ _______ ? if cts function is selected, input on the ctsi pin = l
1.5 precautions for serial i/o (clock-synchronous serial i/o) 18 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. 1.5.3 reception 1. in operating the clock-synchronous serial i/o, operating a transmitter generates a shift clock. fix set- tings for transmission even when using the device only for reception. dummy data is output to the outside from the txdi pin when receiving data. 2. when an internal clock is selected, set the uic1 register (i = 0 to 2) s te bit to 1 (transmission enabled) and write dummy data to the uitb register, and the shift clock will thereby be generated. when an external clock is selected, set the uic1 register (i = 0 to 2) s te bit to 1 and write dummy data to the uitb register, and the shift clock will be generated when the external clock is fed to the clki input pin. 3. when successively receiving data, if all bits of the next receive data are prepared in the uarti receive register while the uic1 register (i = 0 to 2) s re bit = 1 (data present in the uirb register), an overrun error occurs and the uirb register oer bit is set to 1 (overrun error occurred). in this case, because the content of the uirb register is indeterminate, a corrective measure must be taken by programs on the transmit and receive sides so that the valid data before the overrun error occurred will be retransmit- ted. note that when an overrun error occurred, the siric register ir bit does not change state. 4. to receive data in succession, set dummy data in the lower-order byte of the uitb register every time reception is made. 5. when an external clock is selected, the conditions must be met while if the ckpol bit = 0 , the external clock is in the high state; if the ckpol bit = 1 , the external clock is in the low state. ? the re bit of uic1 register= 1 (reception enabled) ? the te bit of uic1 register= 1 (transmission enabled) ? the ti bit of uic1 register= 0 (data present in the uitb register)
1.6 precautions for serial i/o (uart mode, special mode 2) 19 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. 1.6 precautions for serial i/o (uart mode, special mode 2) _______ 1. if a low-level signal is applied to the nmi pin when the tb2sc register ivpcr1 bit = 1 (three-phase _______ _________ output forcible cutoff by input on nmi pin enabled), the rts 2 and clk 2 pins go to a high-impedance state.
1.7 precautions for a-d converter 20 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. 1.7 precautions for a-d converter 1. set adcon0 (except bit 6), adcon1 and adcon2 registers when a-d conversion is stopped (before a trigger occurs). 2. when the vcut bit of adcon1 register is changed from 0 (vref not connected) to 1 (vref con- nected), start a-d conversion after passing 1 s or longer. 3. to prevent noise-induced device malfunction or latchup, as well as to reduce conversion errors, insert capacitors between the av cc , v ref , and analog input pins (ani) each and the av ss pin. similarly, insert a capacitor between the v cc pin and the v ss pin. figure 1.7.1 is an example connection of each pin. 4. make sure the port direction bits for those pins that are used as analog inputs are set to 0 (input mode). also, if the adcon0 register s tgr bit = 1 (external trigger), make sure the port direction bit for ___________ the ad trg pin is set to 0 (input mode). 5. when using key input interrupts, do not use any of the four an 4 to an 7 pins as analog inputs. (a key input interrupt request is generated when the a-d input voltage goes low.) 6. the ad frequency must be 10 mhz or less. without sample-and-hold function, limit the ad frequency to 250kh z or more. with the sample and hold function, limit the ad frequency to 1mh z or more. 7. when changing an a-d operation mode, select analog input pin again in the ch2 to ch0 bits of adcon0 register and the scan1 to scan0 bits of adcon1 register. figure 1.7.1. use of capacitors to reduce noise microcomputer note 1: c1 0.47 f, c2 0.47 f, c3 100pf, c4 0.1 f, c5 0.1 f (reference) note 2: use thick and shortest possible wiring to connect capacitors. v cc1 v ss av cc av ss v ref ani c4 c1 c2 c3 v cc2 v ss c5 ani: ani, an 0 i, and an 2 i (i=0 to 7)
1.7 precautions for a-d converter 21 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. 8. if the cpu reads the adi register (i = 0 to 7) at the same time the conversion result is stored in the adi register after completion of a-d conversion, an incorrect value may be stored in the adi register. this problem occurs when a divide-by-n clock derived from the main clock or a subclock is selected for cpu clock. ? when operating in one-shot or single-sweep mode check to see that a-d conversion is completed before reading the target adi register. (check the adiic register s ir bit to see if a-d conversion is completed.) ? when operating in repeat mode or repeat sweep mode 0 or 1 use the main clock for cpu clock directly without dividing it. 9. if a-d conversion is forcibly terminated while in progress by setting the adcon0 register s adst bit to 0 (a-d conversion halted), the conversion result of the a-d converter is indeterminate. the contents of adi registers irrelevant to a-d conversion may also become indeterminate. if while a-d conversion is underway the adst bit is cleared to 0 in a program, ignore the values of all adi registers. 10. if v cc2 < v cc1 , do not use an 00 to an 07 and an 20 to an 27 as analog input pins.
1.8 precautions for power control 22 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. 1.8 precautions for power control ____________ 1. when exiting stop mode by hardware reset, set reset pin to l until a main clock oscillation is stabilized. 2. insert more than four nop instructions after an wait instruction or a instruction to set the cm10 bit of cm1 register to 1 . when shifting to wait mode or stop mode, an instruction queue reads ahead to the next instruction to halt a program by an wait instruction and an instruction to set the cm10 bit to 1 (all clocks stopped). the next instruction may be executed before entering wait mode or stop mode, de- pending on a combination of instruction and an execution timing. 3. wait until the t su(m-l) elapses or main clock oscillation stabilization time, whichever is longer, before switching the clock source for cpu clock to the main clock. similarly, wait until the sub clock oscillates stably before switching the clock source for cpu clock to the sub clock. 4. suggestions to reduce power consumption (a) ports the processor retains the state of each i/o port even when it goes to wait mode or to stop mode. a current flows in active i/o ports. a pass current flows in input ports that high-impedance state. when entering wait mode or stop mode, set non-used ports to input and stabilize the potential. (b) a-d converter when a-d conversion is not performed, set the vcut bit of adicon1 register to 0 (no v ref connec- tion). when a-d conversion is performed, start the a-d conversion at least 1 s or longer after setting the vcut bit to 1 (v ref connection). (c) d-a converter when not performing d-a conversion, set the dai bit (i=0, 1) of dacon register to 0 (input inhibited) and dai register to 00 16 . (d) stopping peripheral functions use the cm0 register cm02 bit to stop the unnecessary peripheral functions during wait mode. how- ever, because the peripheral function clock (f c32 ) generated from the sub-clock does not stop, this measure is not conducive to reducing the power consumption of the chip. during low speed mode and low power dissipation mode, do not set the cm02 bit to 1 (peripheral function clock stopped when in wait mode) before entering wait mode. (e) switching the oscillation-driving capacity set the driving capacity to low when oscillation is stable. (f) external clock when using an external clock input for the cpu clock, set the cm0 register cm05 bit to 1 (stop). setting the cm05 bit to 1 disables the x out pin from functioning, which helps to reduce the amount of current drawn in the chip. (when using an external clock input, note that the clock remains fed into the chip regardless of how the cm05 bit is set.)
1.9 precautions for external bus 23 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. 1.9 precautions for external bus 1. the external rom version can operate only in the microprocessor mode, connect the cnv ss pin to v cc . 2. when resetting cnvss pin with "h" input, contents of internal rom cannot be read out.
1.10 electric characteristic differences between mask rom and flash memory version microcomputers 24 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. 1.10 electric characteristic differences between mask rom and flash memory version microcomputers flash memory version and mask rom version may have different characteristics, operating margin, noise tolerated dose, noise width dose in electrical characteristics due to internal rom, different layout pattern, etc. when switching to the mask rom version, conduct equivalent tests as system evaluation tests con- ducted in the flush memory version.
1.11 precautions for flash memory version 25 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. 1.11 precautions for flash memory version 1.11.1 precautions for functions to inhibit rewriting flash memory rewrite id codes are stored in addresses 0fffdf 16 , 0fffe3 16 , 0fffeb 16 , 0fffef 16 , 0ffff3 16 , 0ffff7 16 , and 0ffffb 16 . if wrong data are written to theses addresses, the flash memory cannot be read or written in standard serial i/o mode. the romcp register is mapped in address 0fffff 16 . if wrong data is written to this address, the flash memory cannot be read or written in parallel i/o mode. in the flash memory version of microcomputer, these addresses are allocated to the vector addresses (h) of fixed vectors.
1.11 precautions for flash memory version 26 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. 1.11.2 precautions for program command write xx40 16 in the first bus cycle and write data to the write address in the second bus cycle, and an auto program operation (data program and verify) will start. make sure the address value specified in the first bus cycle is the same even address as the write address specified in the second bus cycle.
1.11 precautions for flash memory version 27 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. 1.11.3 precautions for lock bit program command write xx77 16 in the first bus cycle and write xxd0 16 to the uppermost address of a block (even address, however) in the second bus cycle, and the lock bit for the specified block is cleared to 0 . make sure the address value specified in the first bus cycle is the same uppermost block address that is specified in the second bus cycle.
1.11 precautions for flash memory version 28 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. 1.11.4 precautions for stop mode when shifting to stop mode, the following settings are required: ? set the fmr01 bit to 0 (cpu rewrite mode disabled) and disable dma transfers before setting the cm10 bit to 1 (stop mode). ? execute the jmp.b instruction subsequent to the instruction which sets the cm10 bit to 1 (stop mode) example program bset 0, cm1 ; stop mode jmp.b l1 l1: program after returning from stop mode
1.11 precautions for flash memory version 29 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. 1.11.5 precautions for wait mode when shifting to wait mode, set the fmr01 bit to 0 (cpu rewrite mode diabled) before executing the wait instruction.
1.11 precautions for flash memory version 30 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. 1.11.6 precautions for cpu rewrite mode described below are the precautions to be observed when rewriting the flash memory in cpu rewrite mode. 1.11.6.1 operation speed before entering cpu rewrite mode (ew0 or ew1 mode), select 10 mhz or less for bclk using the cm0 register s cm06 bit and cm1 register s cm17 C 6 bits. also, set the pm1 register s pm17 bit to 1 (with wait state).
1.11 precautions for flash memory version 31 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. 1.11.6.2 instructions inhibited against use the following instructions cannot be used in ew0 mode because the flash memory s internal data is referenced: und instruction, into instruction, jmps instruction, jsrs instruction, and brk instruction
1.11 precautions for flash memory version 32 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. 1.11.6.3 interrupts ew0 mode ? any interrupt which has a vector in the variable vector table can be used providing that its vector is transferred into the ram area. _______ ? the nmi and watchdog timer interrupts can be used because the fmr0 register and fmr1 regis- ter are initialized when one of those interrupts occurs. the jump addresses for those interrupt service routines should be set in the fixed vector table. _______ because the rewrite operation is halted when a nmi or watchdog timer interrupt occurs, the rewrite program must be executed again after exiting the interrupt service routine. ? the address match interrupt cannot be used because the flash memory s internal data is refer- enced. ew1 mode ? make sure that any interrupt which has a vector in the variable vector table or address match interrupt will not be accepted during the auto program or auto erase period. ? avoid using watchdog timer interrupts. _______ ? the nmi interrupt can be used because the fmr0 register and fmr1 register are initialized when this interrupt occurs. the jump address for the interrupt service routine should be set in the fixed vector table. _______ because the rewrite operation is halted when a nmi interrupt occurs, the rewrite program must be executed again after exiting the interrupt service routine.
1.11 precautions for flash memory version 33 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. 1.11.6.4 how to access to set the fmr01, fmr02, or fmr11 bit to 1 , write 0 and then 1 in succession. this is necessary to ensure that no interrupts or dma transfers will occur before writing 1 after writing 0 . also only _______ when nmi pin is h level.
1.11 precautions for flash memory version 34 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. 1.11.6.5 writing in the user rom area ew0 mode ? if the power supply voltage drops while rewriting any block in which the rewrite control program is stored, a problem may occur that the rewrite control program is not correctly rewritten and, conse- quently, the flash memory becomes unable to be rewritten thereafter. in this case, standard serial i/o or parallel i/o mode should be used. ew1 mode ? avoid rewriting any block in which the rewrite control program is stored.
1.11 precautions for flash memory version 35 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. 1.11.6.6 dma transfer in ew1 mode, make sure that no dma transfers will occur while the fmr0 register s fmr00 bit = 0 (during the auto program or auto erase period).
1.11 precautions for flash memory version 36 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. 1.11.6.7 writing command and data write the command code and data at even addresses.
1.11 precautions for flash memory version 37 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. 1.11.7 precautions for low power dissipation mode, ring oscillator low power dissipation mode if the cm05 bit is set to 1 (main clock stop), the following commands must not be executed. ? program ? block erase ? erase all unlocked blocks ? lock bit program
1.12 precautions for pll frequency synthesizer 38 mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. 1.12 precautions for pll frequency synthesizer make the supply voltage stable to use the pll frequency synthesizer. for ripple with the supply voltage 5v, keep below 10khz as frequency, below 0.5v (peak to peak) as voltage fluctuation band and below 1v/ms as voltage fluctuation rate. for ripple with the supply voltage 3v, keep below 10khz as frequency, below 0.3v (peak to peak) as voltage fluctuation band and below 0.6v/ms as voltage fluctuation rate.
39 1.13 precautions for programmable i/o ports mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. 1.13 precautions for programmable i/o ports _______ 1. if a low-level signal is applied to the nmi pin when the tb2sc register ivpcr1 bit = 1 (three-phase _______ output forcible cutoff by input on nmi pin enabled), the p7 2 to p7 5 , p8 0 and p8 1 pins go to a high-imped- ance state.
40 2.1 vdet2 detection mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. 2. differences made depending on manufactured time 2.1 vdet2 detection the present version of the products may not detect the vdet2 voltage in the voltage detection circuit prop- erly. therefore, the followings should be noted. (1) when the vc25 bit in the vcr2 register is set to 1 (enabling the ram retention limit detection circuit), the present version may not be reset even if the voltage at the vcc1 input pin drops below vdet2. (2) the wd5 bit in the wdc register may not change properly. supplementary explanation normally, during the stop mode, the vdet3 voltage is not detected, and thus no reset is generated even when the input voltage at the v cc 1 pin drops to vdet3 or less. therefore, if the microcomputer is not reset when the v cc 1 voltage drops below vdet2 due to the reason described in the above no.1, the microcom- puter cannot get out of the stop mode with hardware reset 2.
41 2.2 reset input mitsubishi microcomputer s m16c / 62p grou p single-chip 16-bit cmos microcompute r under development preliminary specifications rev.1.0 specifications in this manual are tentative and subject to change. 2.2 reset input ensure that pin reset must hold valid-low state during powering-up. when using a reset ic, use a cmos type ic. when using an open-drain type reset ic, insert a capacitor between the reset input and vss and a resistor between the input and vcc respectively. the r-c time constant of the capacitor and resistor must provide a low state at least 10 times longer than the vcc rise time.
revision history m16c/62p group usage notes rev. date description page summary 42 1.0 jan/31/y03 figure 1.1.1 is partly revised. the section 1.3 precautions for dmac is added. the section 1.4.1 timers a and b is added. the section 1.4.3.2 timer b (pulse period/pulse width measurement mode is partly revised. the section 1.5.3 reception is partly revised. the section 1.6 precautions for serial i/o (uart mode, special mode 2) is partly revised. the section 1.8 precautions for power control is partly revised. the section 1.11.1 precautions for functions to inhibit rewriting flash memory rewrite is partly revised. the section 1.11.2 precautions for program command is partly revised. the section 1.12 precautions for pll frequency synthesizer is partly revised. 1 8 9 15 18 19 22 25 26 38
mitsubishi semiconductors usage notes reference book m16c/62 (m16c/62p) group february first edition 2003 editioned by committee of editing of mitsubishi semiconductor usage notes reference book published by mitsubishi electric corp., semiconductor marketing division this book, or parts thereof, may not be reproduced in any form without permission of mitsubishi electric corporation. ?2003 mitsubishi electric corporation
u sa g e n otes r e f erence b oo k m1 6c/6 2 ( m16 c /62p ) g rou p n ew p u bli cat i on, e ff ect i ve f e b ruar y 2003 . s pecifications sub j ect to chan g e without notice . ? 2 003 mit su bi s hi ele c tri c co rp o rati o n .

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